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"High Speed 4-Symbol Arithmetic Encoder Architecture for Embedded Zero ..."

Roberto R. Osorio, Bart Vanhoof (2003)

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DOI: 10.1023/A:1022123829466

access: closed

type: Journal Article

metadata version: 2020-05-20

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  - https://dblp.org/rec/journals/vlsisp/OsorioV03
Roberto R. Osorio, Bart Vanhoof:
High Speed 4-Symbol Arithmetic Encoder Architecture for Embedded Zero Tree-Based Compression. J. VLSI Signal Process. 33(3): 267-275 (2003)

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