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"Low Power CMOS Design of Phase Locked Loop for Fastest Frequency ..."

K. Gavaskar, R. Dhivya, R. Dimple Dayana (2022)

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DOI: 10.1007/S11277-022-09654-6

access: closed

type: Journal Article

metadata version: 2022-08-25

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K. Gavaskar, R. Dhivya, R. Dimple Dayana:
Low Power CMOS Design of Phase Locked Loop for Fastest Frequency Acquisition at Various Nanometer Technologies. Wirel. Pers. Commun. 125(3): 2239-2251 (2022)

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