"Advances in Automated Source-Level Debugging of Verilog Designs."

Bernhard Peischl, Naveed Riaz, Franz Wotawa (2008)

> Home

Details and statistics

DOI: 10.1007/978-3-540-79355-7_35

access: closed

type: Part in Book or Collection

metadata version: 2018-11-14

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - series/sci/PeischlRW08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/series/sci/PeischlRW08
Bernhard Peischl, Naveed Riaz, Franz Wotawa:
Advances in Automated Source-Level Debugging of Verilog Designs. New Challenges in Applied Intelligence Technologies 2008: 363-372

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.