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@article{DBLP:journals/vlsisp/Arce-NazarioJR08,
author = {Rafael A. Arce{-}Nazario and
Manuel Jim{\'{e}}nez and
Domingo Rodr{\'{\i}}guez},
title = {Mapping of Discrete Cosine Transforms onto Distributed Hardware Architectures},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {3},
pages = {367--382},
year = {2008},
url = {https://doi.org/10.1007/s11265-008-0239-x},
doi = {10.1007/S11265-008-0239-X},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/Arce-NazarioJR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/AthanasopoulouH08,
author = {Eleftheria Athanasopoulou and
Christoforos N. Hadjicostis},
title = {Bounds on {FSM} Switching Activity},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {3},
pages = {411--418},
year = {2008},
url = {https://doi.org/10.1007/s11265-008-0245-z},
doi = {10.1007/S11265-008-0245-Z},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/AthanasopoulouH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/BaekKS08,
author = {Jae Hyun Baek and
Sung Dae Kim and
Myung Hoon Sunwoo},
title = {{SPOCS:} Application Specific Signal Processor for {OFDM} Communication
Systems},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {3},
pages = {383--397},
year = {2008},
url = {https://doi.org/10.1007/s11265-008-0240-4},
doi = {10.1007/S11265-008-0240-4},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/BaekKS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/BalasaKVPHZC08,
author = {Florin Balasa and
Per Gunnar Kjeldsberg and
Arnout Vandecappelle and
Martin Palkovic and
Qubo Hu and
Hongwei Zhu and
Francky Catthoor},
title = {Storage Estimation and Design Space Exploration Methodologies for
the Memory Management of Signal Processing Applications},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {1-2},
pages = {51--71},
year = {2008},
url = {https://doi.org/10.1007/s11265-008-0244-0},
doi = {10.1007/S11265-008-0244-0},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/BalasaKVPHZC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/Cappello08,
author = {Peter R. Cappello},
title = {Application-specific Processor Architecture: Then and Now},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {1-2},
pages = {197--215},
year = {2008},
url = {https://doi.org/10.1007/s11265-007-0127-9},
doi = {10.1007/S11265-007-0127-9},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/Cappello08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/ChangT08,
author = {Yun{-}Nan Chang and
Ting{-}Chi Tong},
title = {An Efficient Design of {H.264} Inter Interpolator with Bandwidth Optimization},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {3},
pages = {435--448},
year = {2008},
url = {https://doi.org/10.1007/s11265-008-0247-x},
doi = {10.1007/S11265-008-0247-X},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/ChangT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/ChenCCHC08,
author = {Yi{-}Hau Chen and
Shao{-}Yi Chien and
Ching{-}Yeh Chen and
Yu{-}Wen Huang and
Liang{-}Gee Chen},
title = {Analysis and Hardware Architecture Design of Global Motion Estimation},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {3},
pages = {285--300},
year = {2008},
url = {https://doi.org/10.1007/s11265-008-0169-7},
doi = {10.1007/S11265-008-0169-7},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/ChenCCHC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/ChenCCHC08a,
author = {Yi{-}Hau Chen and
Tung{-}Chien Chen and
Shao{-}Yi Chien and
Yu{-}Wen Huang and
Liang{-}Gee Chen},
title = {{VLSI} Architecture Design of Fractional Motion Estimation for {H.264/AVC}},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {3},
pages = {335--347},
year = {2008},
url = {https://doi.org/10.1007/s11265-008-0213-7},
doi = {10.1007/S11265-008-0213-7},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/ChenCCHC08a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/ChenK08,
author = {Yen{-}Kuang Chen and
Sun{-}Yuan Kung},
title = {Trend and Challenge on System-on-a-Chip Designs},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {1-2},
pages = {217--229},
year = {2008},
url = {https://doi.org/10.1007/s11265-007-0129-7},
doi = {10.1007/S11265-007-0129-7},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/ChenK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/HilewitzL08,
author = {Yedidya Hilewitz and
Ruby B. Lee},
title = {Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for
Commodity Microprocessors},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {1-2},
pages = {145--169},
year = {2008},
url = {https://doi.org/10.1007/s11265-008-0212-8},
doi = {10.1007/S11265-008-0212-8},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/HilewitzL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/HugheyB08,
author = {Richard Hughey and
Andrea Di Blas},
title = {Finding the Next Computational Model: Experience with the {UCSC} Kestrel},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {1-2},
pages = {171--186},
year = {2008},
url = {https://doi.org/10.1007/s11265-007-0130-1},
doi = {10.1007/S11265-007-0130-1},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/HugheyB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/JaimeVHZ08,
author = {Francisco J. Jaime and
Julio Villalba and
Javier Hormigo and
Emilio L. Zapata},
title = {Pipelined Architecture for Additive Range Reduction},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {1-2},
pages = {103--112},
year = {2008},
url = {https://doi.org/10.1007/s11265-008-0166-x},
doi = {10.1007/S11265-008-0166-X},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/JaimeVHZ08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/KarkootiRC08,
author = {Marjan Karkooti and
Predrag Radosavljevic and
Joseph R. Cavallaro},
title = {Configurable {LDPC} Decoder Architectures for Regular and Irregular
Codes},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {1-2},
pages = {73--88},
year = {2008},
url = {https://doi.org/10.1007/s11265-008-0221-7},
doi = {10.1007/S11265-008-0221-7},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/KarkootiRC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/KjeldsbergCVPVHA08,
author = {Per Gunnar Kjeldsberg and
Francky Catthoor and
Sven Verdoolaege and
Martin Palkovic and
Arnout Vandecappelle and
Qubo Hu and
Einar J. Aas},
title = {Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing
Applications},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {3},
pages = {301--321},
year = {2008},
url = {https://doi.org/10.1007/s11265-008-0178-6},
doi = {10.1007/S11265-008-0178-6},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/KjeldsbergCVPVHA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/KorahP08,
author = {Reeba Korah and
J. Raja Paul Perinbam},
title = {{FPGA} Implementation of Integer Transform and Quantizer for {H.264}
Encoder},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {3},
pages = {261--269},
year = {2008},
url = {https://doi.org/10.1007/s11265-008-0163-0},
doi = {10.1007/S11265-008-0163-0},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsisp/KorahP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/LeeCV08,
author = {Yong Ki Lee and
Herwin Chan and
Ingrid Verbauwhede},
title = {Design Methodology for Throughput Optimum Architectures of Hash Algorithms
of the MD4-class},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {1-2},
pages = {89--102},
year = {2008},
url = {https://doi.org/10.1007/s11265-008-0168-8},
doi = {10.1007/S11265-008-0168-8},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/LeeCV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/LukSM08,
author = {Wayne Luk and
Yvon Savaria and
Oskar Mencer},
title = {Guest Editorial: 20 Years of {ASAP}},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {1-2},
pages = {1--2},
year = {2008},
url = {https://doi.org/10.1007/s11265-008-0260-0},
doi = {10.1007/S11265-008-0260-0},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/LukSM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/MaroulisIB08,
author = {Dimitrios E. Maroulis and
Dimitrios K. Iakovidis and
Dimitris G. Bariamis},
title = {FPGA-based System for Real-Time Video Texture Analysis},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {3},
pages = {419--433},
year = {2008},
url = {https://doi.org/10.1007/s11265-008-0246-y},
doi = {10.1007/S11265-008-0246-Y},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/MaroulisIB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/Martin08,
author = {Grant Martin},
title = {Multi-Processor SoC-Based Design Methodologies Using Configurable
and Extensible Processors},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {1-2},
pages = {113--127},
year = {2008},
url = {https://doi.org/10.1007/s11265-007-0153-7},
doi = {10.1007/S11265-007-0153-7},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/Martin08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/NelsonHW08,
author = {Brent E. Nelson and
Brad L. Hutchings and
Michael J. Wirthlin},
title = {Design, Debug, Deploy: The Creation of Configurable Computing Applications},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {1-2},
pages = {187--196},
year = {2008},
url = {https://doi.org/10.1007/s11265-008-0167-9},
doi = {10.1007/S11265-008-0167-9},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/NelsonHW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/NeumannSBN08,
author = {Bernd Neumann and
Thorsten von Sydow and
Holger Blume and
Tobias G. Noll},
title = {Application Domain Specific Embedded FPGAs for Flexible ISA-Extension
of ASIPs},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {1-2},
pages = {129--143},
year = {2008},
url = {https://doi.org/10.1007/s11265-008-0211-9},
doi = {10.1007/S11265-008-0211-9},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsisp/NeumannSBN08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/NougarouMA08,
author = {Fran{\c{c}}ois Nougarou and
Daniel Massicotte and
Messaoud Ahmed Ouameur},
title = {Adaptive Duplicated Filters and Interference Canceller for {DS-CDMA}
Systems},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {3},
pages = {349--365},
year = {2008},
url = {https://doi.org/10.1007/s11265-008-0234-2},
doi = {10.1007/S11265-008-0234-2},
timestamp = {Thu, 07 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/NougarouMA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/ParkR08,
author = {Jongsun Park and
Kaushik Roy},
title = {A Low Complexity Reconfigurable {DCT} Architecture to Trade off Image
Quality for Power Consumption},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {3},
pages = {399--410},
year = {2008},
url = {https://doi.org/10.1007/s11265-008-0242-2},
doi = {10.1007/S11265-008-0242-2},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/ParkR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/SchurgersC08,
author = {Curt Schurgers and
Anantha P. Chandrakasan},
title = {Traceback-Based Optimizations for Maximum a Posteriori Decoding Algorithms},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {3},
pages = {231--241},
year = {2008},
url = {https://doi.org/10.1007/s11265-007-0160-8},
doi = {10.1007/S11265-007-0160-8},
timestamp = {Mon, 27 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsisp/SchurgersC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/Swartzlander08,
author = {Earl E. Swartzlander Jr.},
title = {Systolic {FFT} Processors: {A} Personal Perspective},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {1-2},
pages = {3--14},
year = {2008},
url = {https://doi.org/10.1007/s11265-007-0107-0},
doi = {10.1007/S11265-007-0107-0},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/Swartzlander08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/TalaveraJCC08,
author = {Guillermo Talavera and
Murali Jayapala and
Jordi Carrabina and
Francky Catthoor},
title = {Address Generation Optimization for Embedded High-Performance Processors:
{A} Survey},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {3},
pages = {271--284},
year = {2008},
url = {https://doi.org/10.1007/s11265-008-0165-y},
doi = {10.1007/S11265-008-0165-Y},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/TalaveraJCC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/TsaiL08,
author = {Tsung{-}Han Tsai and
Chun{-}Nan Liu},
title = {A Low-Latency Multi-layer Prefix Grouping Technique for Parallel Huffman
Decoding of Multimedia Standards},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {3},
pages = {323--333},
year = {2008},
url = {https://doi.org/10.1007/s11265-008-0210-x},
doi = {10.1007/S11265-008-0210-X},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/TsaiL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/WoodsMM08,
author = {Roger F. Woods and
John V. McCanny and
John G. McWhirter},
title = {From Bit Level Systolic Arrays to {HDTV} Processor Chips},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {1-2},
pages = {35--49},
year = {2008},
url = {https://doi.org/10.1007/s11265-007-0132-z},
doi = {10.1007/S11265-007-0132-Z},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/WoodsMM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/YaoL08,
author = {Kung Yao and
Flavio Lorenzelli},
title = {Systolic Algorithms and Architectures for High-Throughput Processing
Applications},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {1-2},
pages = {15--34},
year = {2008},
url = {https://doi.org/10.1007/s11265-007-0108-z},
doi = {10.1007/S11265-007-0108-Z},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/YaoL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/YuMASLWWMB08,
author = {Zhiyi Yu and
Michael J. Meeuwsen and
Ryan W. Apperson and
Omar Sattari and
Michael A. Lai and
Jeremy W. Webb and
Eric W. Work and
Tinoosh Mohsenin and
Bevan M. Baas},
title = {Architecture and Evaluation of an Asynchronous Array of Simple Processors},
journal = {J. Signal Process. Syst.},
volume = {53},
number = {3},
pages = {243--259},
year = {2008},
url = {https://doi.org/10.1007/s11265-008-0162-1},
doi = {10.1007/S11265-008-0162-1},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/YuMASLWWMB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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