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Publication search results
found 72 matches
- 2024
- Jinook Jung, Jun-Han Choi, Kyoung-Jun Roh, Jaewoo Park, Won-Mook Lim, Tae-Sung Kim, Han-Ki Jeong, Myoungbo Kwak, Jae-Youn Youn, Jeong-Don Ihm, Changsik Yoo, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko:
A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3. IEEE J. Solid State Circuits 59(10): 3307-3316 (2024) - Sung-Yong Cho, Moon-Chul Choi, Jaehyeok Baek, Donggun An, Sanghoon Kim, Daewoong Lee, Seongyeal Yang, Gil-Young Kang, Juseop Park, Kyungho Lee, Hwan-Chul Jung, Gun-hee Cho, ChanYong Lee, Hye-Ran Kim, Yong-Jae Shin, Hanna Park, Sangyong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim, Unhak Lim, Hong-Jun Jin, YoungSeok Lee, Young-Tae Kim, Heonjoo Ha, Jinchan Ahn, Wonju Sung, Yoontaek Jang, Hoyoung Song, Hyodong Ban, TaeHoon Park, Tae-Young Oh, Changsik Yoo, SangJoon Hwang:
13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration. ISSCC 2024: 242-244 - 2023
- Hyuntae Kim, Hyeongmin Seo, Yunseong Jo, Changsik Yoo, Jaeduk Han:
An 8b9b 77.44-Gb/s Noise-Immune Spatial-Delta Coded Transceiver for Short-Reach Memory Interfaces in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 70(4): 1301-1305 (2023) - Hyochang Kim, Hyeongmin Seo, Hyuntae Kim, Changsik Yoo, Jaeduk Han:
A 16-Gb/s/Wire 4-Wire Short-Haul Transceiver With Balanced Single-Ended Signaling (BASES) in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 2799-2803 (2023) - Hyeongmin Seo, Jiyun Han, Kyungmin Kim, Baek-Jin Lim, EunSeok Shin, Youngdon Choi, Hyungjong Ko, Jung-Hwan Choi, Sang-Hyun Lee, Changsik Yoo, Jaeduk Han:
A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 411-415 (2023) - Hyun-A. Ahn, Yoo-Chang Sung, Yong-Hun Kim, Janghoo Kim, Kihan Kim, Donghun Lee, Young-Gil Go, Jae-Woo Lee, Jae-Woo Jung, Yong-Hyun Kim, Garam Choi, Jun-Seo Park, Bo-Hyeon Lee, Jin-Hyeok Baek, Daesik Moon, Daihyun Lim, Seung-Jun Bae, Young-Soo Sohn, Changsik Yoo, Tae-Young Oh:
A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications. A-SSCC 2023: 1-4 - Jinook Jung, Jun-Han Choi, Kyoung-Jun Roh, Jaewoo Park, Won-Mook Lim, Tae-Sung Kim, Han-Ki Jeong, Myoungbo Kwak, Jaeyoun Youn, Jeong-Don Ihm, Changsik Yoo, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko:
A 4ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3. A-SSCC 2023: 1-3 - Daehyun Kwon, Heon Su Jeong, Jaemin Choi, Wijong Kim, Jae Woong Kim, Junsub Yoon, Jungmin Choi, Sanguk Lee, Hyunsub Norbert Rie, Jin-Il Lee, Jongbum Lee, Taeseong Jang, JunHyung Kim, Sanghee Kang, Jung-Bum Shin, Yanggyoon Loh, Chang-Yong Lee, Junmyung Woo, Hye-Seung Yu, Changhyun Bae, Reum Oh, Young-Soo Sohn, Changsik Yoo, Jooyoung Lee:
A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL. ISSCC 2023: 412-413 - Seungki Hong, Dongha Kim, Jaehyung Lee, Reum Oh, Changsik Yoo, Sang Joon Hwang, Jooyoung Lee:
DSAC: Low-Cost Rowhammer Mitigation Using In-DRAM Stochastic and Approximate Counting Algorithm. CoRR abs/2302.03591 (2023) - 2022
- Junsik Kim, Hyungwha Jeong, Jeongmok Cho, Changsik Pak, Tae Suk Oh, Joon Pio Hong, Soonchul Kwon, Jisang Yoo:
Numerical Approach to Facial Palsy Using a Novel Registration Method with 3D Facial Landmark. Sensors 22(17): 6636 (2022) - Dae-Hyun Kim, Byungkyu Song, Hyun-A. Ahn, Woongjoon Ko, Sung-Geun Do, Seokjin Cho, Kihan Kim, Seung-Hoon Oh, Hye-Yoon Joo, Geuntae Park, Jin-Hun Jang, Yong-Hun Kim, Donghun Lee, Jaehoon Jung, Yongmin Kwon, Youngjae Kim, Jaewoo Jung, Seongil O, Seoulmin Lee, Jaeseong Lim, Junho Son, Jisu Min, Haebin Do, Jaejun Yoon, Isak Hwang, Jinsol Park, Hong Shim, Seryeong Yoon, Dongyeong Choi, Jihoon Lee, Soohan Woo, Eunki Hong, Junha Choi, Jae-Sung Kim, Sangkeun Han, Jong-Min Bang, Bokgue Park, Jang-Hoo Kim, Seouk-Kyu Choi, Gong-Heum Han, Yoo-Chang Sung, Wonil Bae, Jeong-Don Lim, Seungjae Lee, Changsik Yoo, Sang Joon Hwang, Jooyoung Lee:
A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process. ISSCC 2022: 448-450 - 2021
- Eun Seong Kim, Ganbold Enkhzaya, Hyeon-Sik Hwang, Ji-Ho Han, Chang-Sik Kim, Jaewoo Shin, Young-Ro Yoon, Nam-Young Kim:
Highly Efficient Transfection Effect of Transdermal Drug Delivery via Skin by Hybrid Bipolar Arc Plasma Stimulation and Dual Pulse Electroporation Technique. IEEE Access 9: 24071-24078 (2021) - Jeongpyo Park, Min-Gyu Jeong, Jin-Gyu Kang, Changsik Yoo:
Solar Energy-Harvesting Buck-Boost Converter With Battery-Charging and Battery-Assisted Modes. IEEE Trans. Ind. Electron. 68(3): 2163-2172 (2021) - Hojun Yoon, Wonjoo Jung, Jaewoo Park, Jindo Byun, Hyungmin Jin, Hyunyoon Cho, Youngmin Kim, Baek-Jin Lim, Young-Chul Cho, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko, Changsik Yoo, Sang-Hyun Lee:
A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics. ESSCIRC 2021: 463-466 - Seunghwan Hong, Chang-Hyun Bae, Yoo-Chang Sung, Jaewoong Kim, Junsub Yoon, Sangwoo Kim, Jin-Hyeok Baek, Cheongryong Cho, Useung Shin, Sang-Kyeom Kim, Hwan-Chul Jung, Ho-Jun Chang, Jang-Hoo Kim, Jeongsik Hwang, Hyunki Kim, Ki-Won Lee, Dongmin Kim, Han-Ki Jeong, Myung-O. Kim, Kyomin Sohn, Jeong-Don Ihm, Changsik Yoo, Sang Joon Hwang:
A Reflection and Crosstalk Canceling Continuous-Time Linear Equalizer for High-Speed DDR SDRAM. VLSI Circuits 2021: 1-2 - 2020
- Jinsol Yang, Sohee Kwon, Sang-Hun Bae, Kyoung Mii Park, Changsik Yoon, Ji-Hyun Lee, Chaok Seok:
GalaxySagittarius: Structure- and Similarity-Based Prediction of Protein Targets for Druglike Compounds. J. Chem. Inf. Model. 60(6): 3246-3254 (2020) - Kyungmin Kim, Changsik Yoo:
Time-Domain Operational Amplifier With Voltage-Controlled Oscillator and Its Application to Active-RC Analog Filter. IEEE Trans. Circuits Syst. II Express Briefs 67-II(3): 415-419 (2020) - Hyochang Kim, Changsik Yoo:
A 6-Gb/s Wireline Receiver With Intrapair Skew Compensation and Three-Tap Decision-Feedback Equalizer in 28-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 28(5): 1107-1117 (2020) - KyungHee Lee, Jaebok Park, Seung-mok Yoo, Seok Jin Yoon, Chang-Sik Cho:
An Implementation of NNEF-Darknet Neural Network Model Converter. ICTC 2020: 1186-1188 - 2019
- Jin-Gyu Kang, Jeongpyo Park, Min-Gyu Jeong, Changsik Yoo:
A Time-Domain-Controlled Current-Mode Buck Converter With Wide Output Voltage Range. IEEE J. Solid State Circuits 54(3): 865-873 (2019) - Donghyeok Jeong, Changsik Yoo:
A 4-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Stochastic Quantizer and Digital Accumulator. IEEE Trans. Circuits Syst. II Express Briefs 66-II(7): 1124-1128 (2019) - Min-Gyu Jeong, Jin-Gyu Kang, Jeongpyo Park, Changsik Yoo:
A Current-Mode Hysteretic Buck Converter With Multiple-Reset RC-Based Inductor Current Sensor. IEEE Trans. Ind. Electron. 66(11): 8445-8453 (2019) - Jin-Gyu Kang, Min-Gyu Jeong, Jeongpyo Park, Changsik Yoo:
Time-Based Digital LDO Regualtor with Fractionally Controlled Power Transistor Strength and Fast Transient Response. A-SSCC 2019: 45-48 - Seung-mok Yoo, Chang-Sik Cho, KyungHee Lee, Jaebok Park, Seok Jin, Young-Woon Lee, Byung-Gyu Kim:
Structure of Deep Learning Inference Engines for Embedded Systems. ICTC 2019: 920-922 - 2018
- Baek-Jin Lim, Changsik Yoo:
Continuous-time linear equalizer with automatic boosting gain adaptation and input offset cancellation. Int. J. Circuit Theory Appl. 46(11): 2151-2159 (2018) - Jin-Gyu Kang, Min-Gyu Jeong, Jeongpyo Park, Changsik Yoo:
A 10MHz time-domain-controlled current-mode buck converter with 8.5% to 93% switching duty cycle. ISSCC 2018: 424-426 - 2017
- Min-Ki Jeon, Won-Jun Yoo, Chan-Gyu Kim, Changsik Yoo:
A Stochastic Flash Analog-to-Digital Converter Linearized by Reference Swapping. IEEE Access 5: 23046-23051 (2017) - Hyochang Kim, Ook Kim, Changsik Yoo:
Duty-cycle and phase spacing error correction circuit for high-speed serial link. IEICE Electron. Express 14(12): 20170497 (2017) - Min-Ki Jeon, Changsik Yoo:
A simultaneously bidirectional inductively coupled link in a 0.13-µm CMOS technology. Int. J. Circuit Theory Appl. 45(4): 515-529 (2017) - 2016
- Young-Jin Moon, Jeongpyo Park, Min-Gyu Jeong, Sang-Hyun Kim, Jin-Gyu Kang, Dong-Zo Kim, Changsik Yoo:
Wireless power charger for wearable medical devices with in-band communication. Int. J. Circuit Theory Appl. 44(8): 1483-1493 (2016)
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