• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
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  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 13 matches

• 2007
• 
  Shoko Ohteru, Keiji Kishine, Haruhiko Ichino:
  MAC protocol based on cross-layer design methodology for fast link in wireless communication systems. IEICE Electron. Express 4(19): 593-599 (2007)
• 2005
• 
  Kazuhiko Terada, Kenji Kawai, Osamu Ishida, Keiji Kishine, Noboru Iwasaki, Haruhiko Ichino:
  Physical Layer OAM&P Signaling Method for 10 Gbit/s Ethernet Transport over Optical Networks. IEICE Trans. Commun. 88-B(10): 3952-3961 (2005)
• 2004
• 
  Keiji Kishine, Kyoko Fujimoto, Satomi Kusanagi, Haruhiko Ichino:
  PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits. IEEE J. Solid State Circuits 39(5): 740-750 (2004)
• 2002
• 
  Keiji Kishine, Kiyoshi Ishii, Haruhiko Ichino:
  Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX. IEEE J. Solid State Circuits 37(1): 38-50 (2002)
• 2000
• 
  Kenji Kawai, Haruhiko Ichino:
  A 0.6-W 10-Gb/s SONET/SDH bit-error-rate monitoring LSI. IEEE J. Solid State Circuits 35(12): 1988-1991 (2000)
• 
  Kiyoshi Ishii, Keiji Kishine, Haruhiko Ichino:
  A jitter suppression technique for a 2.48832 Gb/s clock and data recovery circuit. ISCAS 2000: 261-264
• 1999
• 
  Kenji Kawai, Keiichi Koike, Yuichiro Takei, Akira Onozawa, Hitoshi Obara, Haruhiko Ichino:
  A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design. IEEE J. Solid State Circuits 34(1): 12-17 (1999)
• 
  Keiji Kishine, Noboru Ishihara, Ken-ichi Takiguchi, Haruhiko Ichino:
  A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs. IEEE J. Solid State Circuits 34(6): 805-812 (1999)
• 1998
• 
  Keiichi Koike, Kenji Kawai, Akira Onozawa, Yuichiro Takei, Yoshiji Kobayashi, Haruhiko Ichino:
  High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing. IEEE J. Solid State Circuits 33(10): 1536-1544 (1998)
• 1997
• 
  Keiji Kishine, Yoshiji Kobayashi, Haruhiko Ichino:
  A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic. IEEE J. Solid State Circuits 32(2): 215-221 (1997)
• 1995
• 
  Kiyoshi Ishii, Haruhiko Ichino, Minoru Togashi, Yoshiji Kobayashi, Chikara Yamaguchi:
  Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops. IEEE J. Solid State Circuits 30(1): 19-24 (1995)
• 1994
• 
  Kiyoshi Ishii, Haruhiko Ichino, Yoshiji Kobayashi, Chikara Yamaguchi:
  High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology. IEEE J. Solid State Circuits 29(5): 546-550 (1994)
• 
  Kiyoshi Ishii, Haruhiko Ichino, Chikara Yamaguchi:
  Maximum operating frequency in Si bipolar master-slave toggle flip-flop circuit. IEEE J. Solid State Circuits 29(7): 754-760 (1994)