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Publication search results
found 59 matches
- 2023
- Piotr Patronik, Stanislaw J. Piestrak:
Design of reverse converters for the general RNS 3-moduli set {2k, 2n - 1, 2n + 1}. EURASIP J. Adv. Signal Process. 2023(1): 92 (2023) - 2018
- Piotr Patronik, Stanislaw J. Piestrak:
Correction to: Design of Reverse Converters for a New Flexible RNS Five-Moduli Set {2k, 2n-1, 2n+1, 2n+1-1, 2n-1-1} (n Even). Circuits Syst. Signal Process. 37(11): 5197 (2018) - Piotr Patronik, Stanislaw J. Piestrak:
Design of RNS Reverse Converters with Constant Shifting to Residue Datapath Channels. J. Signal Process. Syst. 90(3): 323-339 (2018) - 2017
- Piotr Patronik, Stanislaw J. Piestrak:
Design of Reverse Converters for a New Flexible RNS Five-Moduli Set {2k, 2n-1, 2n+1, 2n+1-1, 2n-1-1} (n Even). Circuits Syst. Signal Process. 36(11): 4593-4614 (2017) - Piotr Patronik, Stanislaw J. Piestrak:
Hardware/Software Approach to Designing Low-Power RNS-Enhanced Arithmetic Units. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(5): 1031-1039 (2017) - Piotr Patronik, Stanislaw J. Piestrak:
Design of residue generators with CLA/compressor trees and multi-bit EAC. LASCAS 2017: 1-4 - 2016
- Piotr Patronik, Stanislaw J. Piestrak:
Design of a low-power RNS-enhanced arithmetic unit. LASCAS 2016: 151-154 - 2015
- Stanislaw J. Piestrak:
A note on RNS architectures for the implementation of the diagonal function. Inf. Process. Lett. 115(4): 453-457 (2015) - B. Chagun Basha, Sébastien Pillement, Stanislaw J. Piestrak:
Fault-aware configurable logic block for reliable reconfigurable FPGAs. ISCAS 2015: 2732-2735 - Stanislaw J. Piestrak, Piotr Patronik:
Fault-tolerant implementation of direct FIR filters protected using residue codes. NORCAS 2015: 1-4 - 2014
- Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Private reliability environments for efficient fault-tolerance in CGRAs. Des. Autom. Embed. Syst. 18(3-4): 295-327 (2014) - Syed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement:
Design of the coarse-grained reconfigurable architecture DART with on-line error detection. Microprocess. Microsystems 38(2): 124-136 (2014) - Piotr Patronik, Stanislaw J. Piestrak:
Design of Reverse Converters for General RNS Moduli Sets {2k, 2n-1, 2n+1, 2n+1-1} and {2k, 2n-1, 2n+1, 2n-1-1} (n even). IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(6): 1687-1700 (2014) - Piotr Patronik, Stanislaw J. Piestrak:
Design of Reverse Converters for the New RNS Moduli Set {2n+1, 2n-1, 2n, 2n-1+1} (n odd). IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(12): 3436-3449 (2014) - B. Chagun Basha, Stanislaw J. Piestrak, Sébastien Pillement:
Built-in 3-Dimensional Hamming Multiple-Error Correcting Scheme to Mitigate Radiation Effects in SRAM-Based FPGAs. ARC 2014: 254-261 - Stanislaw J. Piestrak, Piotr Patronik:
Design of Fault-Secure Transposed FIR Filters Protected Using Residue Codes. DSD 2014: 575-582 - 2013
- Hung-Manh Pham, Sébastien Pillement, Stanislaw J. Piestrak:
Low-Overhead Fault-Tolerance Technique for a Dynamically Reconfigurable Softcore Processor. IEEE Trans. Computers 62(6): 1179-1192 (2013) - Syed M. A. H. Jafri, Stanislaw J. Piestrak, Kolin Paul, Ahmed Hemani, Juha Plosila, Hannu Tenhunen:
Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs. DSD 2013: 525-534 - Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Implementation and evaluation of configuration scrubbing on CGRAs: A case study. ISSoC 2013: 1-8 - 2012
- Piotr Patronik, Krzysztof S. Berezowski, Janusz Biernat, Stanislaw J. Piestrak, Aviral Shrivastava:
Design of an RNS reverse converter for a new five-moduli special set. ACM Great Lakes Symposium on VLSI 2012: 67-70 - 2011
- Muhammad Moazam Azeem, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement:
Error recovery technique for coarse-grained reconfigurable architectures. DDECS 2011: 441-446 - Stanislaw J. Piestrak:
Design of multi-residue generators using shared logic. ISCAS 2011: 1435-1438 - Piotr Patronik, Krzysztof S. Berezowski, Stanislaw J. Piestrak, Janusz Biernat, Aviral Shrivastava:
Fast and energy-efficient constant-coefficient FIR filters using residue number system. ISLPED 2011: 385-390 - 2010
- Stanislaw J. Piestrak, Sébastien Pillement, Olivier Sentieys:
Comments on "A Low-Power Dependable Berger Code for Fully Asymmetric Communication". IEEE Commun. Lett. 14(8): 761-763 (2010) - Stanislaw J. Piestrak, Sébastien Pillement, Olivier Sentieys:
Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication. IEEE Trans. Circuits Syst. II Express Briefs 57-II(10): 777-781 (2010) - Stanislaw J. Piestrak:
On Reducing Error Rate of Data Protected Using Systematic Unordered Codes in Asymmetric Channels. DSD 2010: 133-140 - Stanislaw J. Piestrak:
Design of cost-efficient multipliers modulo 2a-1. ISCAS 2010: 4093-4096 - Syed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement:
Design of a fault-tolerant coarse-grained. ISQED 2010: 845-852 - 2009
- Houssein Jaber, Fabrice Monteiro, Stanislaw J. Piestrak, Abbas Dandache:
Design of parallel fault-secure encoders for systematic cyclic block transmission codes. Microelectron. J. 40(12): 1686-1697 (2009) - Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shrivastava, Stanislaw J. Piestrak:
Exploiting residue number system for power-efficient digital signal processing in embedded processors. CASES 2009: 19-28
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