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Publication search results
found 37 matches
- 2024
- Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri:
Built-in Self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs. Integr. 94: 102088 (2024) - 2023
- Tapobrata Dhar, Ranit Das, Chandan Giri, Surajit Kumar Roy:
Threshold Analysis Using Probabilistic Xgboost Classifier for Hardware Trojan Detection. J. Electron. Test. 39(4): 447-463 (2023) - Sourav Ghosh, Surajit Kumar Roy, Chandan Giri:
Fault Detection and Diagnosis of DMFB Using Concurrent Electrodes Actuation. J. Electron. Test. 39(1): 89-102 (2023) - Surajit Giri, Siddhartha Banerjee:
Performance analysis of annotation detection techniques for cyber-bullying messages using word-embedded deep neural networks. Soc. Netw. Anal. Min. 13(1): 23 (2023) - Sourav Ghosh, Surajit Kumar Roy, Chandan Giri:
Cost Effective Single Target Sample Preparation on Digital Microfluidic Biochip. iSES 2023: 81-86 - 2022
- Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri:
A Cost-Effective Built-In Self-Test Mechanism for Post-Manufacturing TSV Defects in 3D ICs. ACM J. Emerg. Technol. Comput. Syst. 18(4): 70:1-70:23 (2022) - Subhajit Chatterjee, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman:
Frequency-scaled thermal-aware test scheduling for 3D ICs using machine learning based temperature estimation. Microelectron. J. 128: 105535 (2022) - Sonu Kumar, Giriraj Amarnath, Surajit Ghosh, Edward Park, Triambak Baghel, Jingyu Wang, Malay Pramanik, Devesh Belbase:
Assessing the Performance of the Satellite-Based Precipitation Products (SPP) in the Data-Sparse Himalayan Terrain. Remote. Sens. 14(19): 4810 (2022) - 2021
- Sourav Ghosh, Surajit Kumar Roy, Chandan Giri:
Testing and Diagnosis of Digital Microfluidic Biochips using Multiple Droplets. J. Electron. Test. 37(1): 109-126 (2021) - Tapobrata Dhar, Surajit Kumar Roy, Chandan Giri:
Hardware Trojan Horse Detection through Improved Switching of Dormant Nets. ACM J. Emerg. Technol. Comput. Syst. 17(3): 33:1-33:22 (2021) - Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri:
TSV-Cluster Defect Tolerance Using Tree-Based Redundancy for Yield Improvement of 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8): 1500-1510 (2021) - 2020
- Subhajit Chatterjee, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman:
An Efficient Test Scheduling to Co-optimize Test Time and Peak Power for 3D ICs. ISDCS 2020: 1-6 - 2019
- Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri:
Identification of Random/Clustered TSV Defects in 3D IC During Pre-Bond Testing. J. Electron. Test. 35(5): 741-759 (2019) - Sourav Ghosh, Dolan Maity, Arijit Chowdhury, Surajit Kumar Roy, Chandan Giri:
Iterative Parallel Test to Detect and Diagnose Multiple Defects for Digital Microfluidic Biochip. ATS 2019: 147-152 - Tapobrata Dhar, Surajit Kumar Roy, Chandan Giri:
Hardware Trojan Detection by Stimulating Transitions in Rare Nets. VLSID 2019: 537-538 - 2018
- Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman:
Identification of Faulty TSV with a Built-In Self-Test Mechanism. ATS 2018: 1-6 - Tapobrata Dhar, Surajit Kumar Roy, Chandan Giri:
Detecting Hardware Trojans by Reducing Rarity of Transitions in ICs. VDAT 2018: 173-185 - Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri:
Identification of Faulty TSVs in 3D IC During Pre-Bond Testing. VLSID 2018: 109-114 - 2017
- Sudeep Ghosh, Surajit Kumar Roy, Hafizur Rahaman, Chandan Giri:
TSV repairing for 3D ICs using redundant TSV. ISED 2017: 1-5 - Surajit Kumar Roy, Chandan Giri:
Design-for-test and test time optimization for 3D SOCs. ITC 2017: 1-10 - Subhajit Chatterjee, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman:
Modeling and Analysis of Transient Heat for 3D IC. VDAT 2017: 365-375 - Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri:
Faulty TSVs Identification in 3D IC Using Pre-bond Testing. VDAT 2017: 805-812 - 2016
- Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman:
Optimization of Test Wrapper for TSV Based 3D SOCs. J. Electron. Test. 32(5): 511-529 (2016) - 2015
- Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman:
Optimisation of test architecture in three-dimensional stacked integrated circuits for partial stack/complete stack using hard system-on-chips. IET Comput. Digit. Tech. 9(5): 268-274 (2015) - Sumit Dhuwalia, Nikhil Khemka, Prince Gupta, Surajit Kumar Roy, Chandan Giri:
Test Time Optimization for 3D-SICs Having Multiple Towers. iNIS 2015: 131-136 - Surajit Kumar Roy, Kaustav Roy, Chandan Giri, Hafizur Rahaman:
Recovery of faulty TSVs in 3D ICs. ISQED 2015: 533-536 - Surajit Kumar Roy, Supriyo Mandal, Chandan Giri, Hafizur Rahaman:
A thermal estimation model for 3D IC using liquid cooled microchannels and thermal TSVs. VLSI-SoC 2015: 122-127 - 2014
- Surajit Kumar Roy, Payel Ghosh, Hafizur Rahaman, Chandan Giri:
Session Based Core Test Scheduling for 3D SOCs. ISVLSI 2014: 196-201 - 2013
- Surajit Kumar Roy, Sobitri Chatterjee, Chandan Giri, Hafizur Rahaman:
Faulty TSVs identification and recovery in 3D stacked ICs during pre-bond testing. 3DIC 2013: 1-6 - Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman:
Optimizing test architecture of 3D stacked ICs for partial stack/complete stack using hard SoCs. IDT 2013: 1-3
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