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Publication search results
found 16 matches
- 2023
- Taehwan Moon, Hyun Jae Lee, Seung Geol Nam, Hagyoul Bae, Duk-Hyun Choe, Sanghyun Jo, Yun Seong Lee, Yoonsang Park, J. Joshua Yang, Jinseong Heo:
Parallel synaptic design of ferroelectric tunnel junctions for neuromorphic computing. Neuromorph. Comput. Eng. 3(2): 24001 (2023) - 2014
- Taehwan Oh, Hariprasath Venkatram, Un-Ku Moon:
A Time-Based Pipelined ADC Using Both Voltage and Time Domain Information. IEEE J. Solid State Circuits 49(4): 961-971 (2014) - Hariprasath Venkatram, Taehwan Oh, Kazuki Sobue, Koichi Hamashita, Un-Ku Moon:
A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier. VLSIC 2014: 1-2 - 2013
- Hariprasath Venkatram, Benjamin P. Hershberg, Taehwan Oh, Manideep Gande, Kazuki Sobue, Koichi Hamashita, Un-Ku Moon:
Parallel gain enhancement technique for switched-capacitor circuits. CICC 2013: 1-4 - 2012
- Jon Guerber, Hariprasath Venkatram, Taehwan Oh, Un-Ku Moon:
Enhanced SAR ADC energy efficiency from the early reset merged capacitor switching algorithm. ISCAS 2012: 2361-2364 - Taehwan Oh, Hariprasath Venkatram, Jon Guerber, Un-Ku Moon:
Correlated jitter sampling for jitter cancellation in pipelined TDC. ISCAS 2012: 810-813 - Hariprasath Venkatram, Taehwan Oh, Jon Guerber, Un-Ku Moon:
Class A+ amplifier with controlled positive feedback for discrete-time signal processing circuits. ISCAS 2012: 428-431 - Manideep Gande, Nima Maghari, Taehwan Oh, Un-Ku Moon:
A 71dB dynamic range third-order ΔΣ TDC using charge-pump. VLSIC 2012: 168-169 - Taehwan Oh, Nima Maghari, Un-Ku Moon:
A 5MHz BW 70.7dB SNDR noise-shaped two-step quantizer based ΔΣ ADC. VLSIC 2012: 162-163 - 2011
- Taehwan Oh, Nima Maghari, David Gubbins, Un-Ku Moon:
Analysis of Residue Integration Sampling With Improved Jitter Immunity. IEEE Trans. Circuits Syst. II Express Briefs 58-II(7): 417-421 (2011) - 2009
- Moon Ki Jung, Hyundeok Cho, Taehwan Roh, Kunwoo Lee:
Integrated Framework for Vehicle Interior Design Using Digital Human Model. J. Comput. Sci. Technol. 24(6): 1149-1161 (2009) - 2008
- Tae-Hwan Oh, Ho-Young Lee, Ju-Hwa Kim, Ho-Jin Park, Kyoung-Ho Moon, Jae-Whui Kim, Hae-Seung Lee:
A 16b 10MS/s digitally self-calibrated ADC with time constant control. CICC 2008: 113-116 - 2006
- Tae-Hwan Oh, Sang-Min Yoo, Kyoung-Ho Moon, Jae-Whui Kim:
A 3.0 V 72mW 10b 100 MSample/s Nyquist-rate CMOS pipelined ADC in 0.54 mm2. ISCAS 2006 - Sang-Min Yoo, Tae-Hwan Oh, Ho-Young Lee, Kyung-Ho Moon, Jae-Whui Kim:
A 3.0V 12b 120 Msample/s CMOS pipelined ADC. ISCAS 2006 - 2002
- Sang-Min Yoo, Tae-Hwan Oh, Jung-Woong Moon, Seung-Hoon Lee, Un-Ku Moon:
A 2.5 V 10 b 120 MSample/s CMOS pipelined ADC with high SFDR. CICC 2002: 441-444 - Chul-Hong Park, Soo-Han Choi, Sang-Uhk Rhie, Dong-Hyun Kim, Jun-Seong Park, Tae-Hwang Jang, Ji-Soong Park, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong:
A Hybrid PPC Method Based on the Empirical Etch Model for the 0.14µm DRAM Generation and Beyond. ISQED 2002: 143-147
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