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ORCIDIEEE Journal of Solid-State Circuits, Volume 49
Volume 49, Number 1, January 2014
- Michael P. Flynn:
New Associate Editor. 3 - Timothy C. Fischer, Byeong-Gyu Nam
, Leland Chang, Tadahiro Kuroda, Michiel A. P. Pertijs:
Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions. 4-8 - James D. Warnock, Yuen H. Chan, Hubert Harrer, Sean M. Carey, Gerard Salem, Doug Malone, Ruchir Puri, Jeffrey A. Zitz, Adam Jatkowski, Gerald Strevig, Ayan Datta, Anne Gattiker, Aditya Bansal, Guenter Mayer, Yiu-Hing Chan, Mark D. Mayo, David L. Rude, Leon J. Sigal, Thomas Strach, Howard H. Smith, Huajun Wen, Pak-kin Mak, Chung-Lung Kevin Shum, Donald W. Plass, Charles F. Webb:
Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module. 9-18 - Jason Hart, Hoyeol Cho, Yuefei Ge, Gregory Gruber, Dawei Huang, Changku Hwang, Daisy Jian, Timothy Johnson, Georgios K. Konstadinidis, Venkatram Krishnaswamy, Lance Kwong, Robert P. Masleid, Rakesh Mehta, Umesh Nawathe, Aparna Ramachandran, Harikaran Sathianathan, Yongning Sheng, Jinuk Luke Shin, Sebastian Turullols, Zuxu Qin, King C. Yen:
A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm. 19-31 - Ryuji Kan, Tomohiro Tanaka, Go Sugizaki, Kinya Ishizaka, Ryuichi Nishiyama, Sota Sakabayashi, Yoichi Koyanagi, Ryuji Iwatsuki, Kazumi Hayasaka, Taiki Uemura, Gaku Ito, Yoshitomo Ozeki, Hiroyuki Adachi, Kazuhiro Furuya, Tsuyoshi Motokurumada:
The 10th Generation 16-Core SPARC64™ Processor for Mission Critical UNIX Server. 32-40 - Weiwu Hu, Liang Yang, Bao-Xia Fan, Huandong Wang, Yunji Chen:
An 8-Core MIPS-Compatible Processor in 32/28 nm Bulk CMOS. 41-49 - Ahmed Musa, Wei Deng, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa:
A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration. 50-60 - Mehul Tikekar, Chao-Tsung Huang, Chiraag Juvekar, Vivienne Sze, Anantha P. Chandrakasan:
A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications. 61-72 - Daisuke Miyashita, Ryo Yamaki, Kazunori Hashiyoshi, Hiroyuki Kobayashi, Shouhei Kousai, Yukihito Oowaki, Yasuo Unekawa:
An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing. 73-83 - Paul N. Whatmough, Shidhartha Das, David M. Bull:
A Low-Power 1-GHz Razor FIR Accelerator With Time-Borrow Tracking Pipeline and Approximate Error Correction in 65-nm CMOS. 84-94 - Sudhanshu Khanna, Steven Bartling, Michael Clinton, Scott R. Summerfelt, John A. Rodriguez, Hugh P. McAdams:
An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at VDD = 0 V Achieving Zero Leakage With < 400-ns Wakeup Time for ULP Applications. 95-106 - Mahmut E. Sinangil, Anantha P. Chandrakasan:
Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9× Lower Energy/Access. 107-117 - Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa:
A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit. 118-126 - Michael Bucher, Ravi T. Kollipara, Bruce Su, Liji Gopalakrishnan, Kashinath Prabhu, Pravin Kumar Venkatesan, Kambiz Kaviani, Barry Daly, William F. Stonecypher, Wayne D. Dettloff, Teva Stone, Fred Heaton, Yi Lu, Chris J. Madden, Sanath Bangalore, John C. Eble, Nhat Nguyen, Lei Luo:
A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems. 127-139 - Tz-Yi Liu, Tian Hong Yan, Roy Scheuerlein, Yingchang Chen, Jeffrey KoonYee Lee, Gopinath Balakrishnan, Gordon Yee, Henry Zhang, Alex Yap, Jingwen Ouyang, Takahiko Sasaki, Ali Al-Shamma, Chin-Yu Chen, Mayank Gupta, Greg Hilton, Achal Kathuria, Vincent Lai, Masahide Matsumoto, Anurag Nigam, Anil Pai, Jayesh Pakhale, Chang Hua Siau, Xiaoxia Wu, Yibo Yin, Nicolas Nagel, Yoichiro Tanaka, Masaaki Higashitani, Tim Minvielle, Chandu Gorla, Takayuki Tsukamoto, Takeshi Yamaguchi, Mutsumi Okajima, Takayuki Okamura, Satoru Takase, Hirofumi Inoue, Luca Fasoli:
A 130.7-mm2 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology. 140-153 - Takashi Kono, Takashi Ito, Tamaki Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Yoshiyuki Kawashima, Hideto Hidaka, Tadaaki Yamauchi:
40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170°C. 154-166 - Kiseok Song, Unsoo Ha, Jaehyuk Lee, Kyeongryeol Bong, Hoi-Jun Yoo:
An 87-mA · min Iontophoresis Controller IC With Dual-Mode Impedance Sensor for Patch-Type Transdermal Drug Delivery System. 167-178 - Yuki Maruyama, Jordana Blacksberg, Edoardo Charbon:
A 1024 × 8, 700-ps Time-Gated SPAD Line Sensor for Planetary Surface Exploration With Laser Raman Spectroscopy and LIBS. 179-189 - Max M. Shulaker, Jelle Van Rethy, Gage Hills, Hai Wei, Hong-Yu Chen, Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra:
Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs. 190-201 - Masood Qazi, Ajith Amerasekera, Anantha P. Chandrakasan:
A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-µm CMOS for Nonvolatile Processing in Digital Systems. 202-211 - David Ruffieux, Nicola Scolari, Frédéric Giroud, Thanh-Chau Le, Silvio Dalla Piazza, Felix Staub, Kai Zoschke, Charles Alix Manier, Hermann Oppermann, Tommi Suni, James Dekker, Giorgio Allegato:
A Versatile Timing Microsystem Based on Wafer-Level Packaged XTAL/BAW Resonators With Sub-µW RTC Mode and Programmable HF Clocks. 212-222 - Atsutake Kosuge, Wataru Mizuhara, Tsunaaki Shidei, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda:
A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler. 223-231 - Wei-Ming Chen, Herming Chiueh, Tsan-Jieh Chen, Chia-Lun Ho, Chi Jeng, Ming-Dou Ker, Chun-Yu Lin, Ya-Chun Huang, Chia-Wei Chou, Tsun-Yuan Fan, Ming-Seng Cheng, Yue-Loong Hsin, Sheng-Fu Liang, Yu-Lin Wang, Fu-Zen Shaw, Yu-Hsing Huang, Chia-Hsiang Yang, Chung-Yu Wu:
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control. 232-247 - Carolina Mora Lopez, Alexandru Andrei, Srinjoy Mitra, Marleen Welkenhuysen, Wolfgang Eberle, Carmen Bartic, Robert Puers, Refet Firat Yazicioglu, Georges G. E. Gielen:
An Implantable 455-Active-Electrode 52-Channel CMOS Neural Probe. 248-261 - Vladimir P. Petkov, Ganesh K. Balachandran, Jochen Beintner:
A Fully Differential Charge-Balanced Accelerometer for Electronic Stability Control. 262-270 - Mohammad Alhawari, Nadya Albelooshi, Michael H. Perrott:
A 0.5 V < 4 µW CMOS Light-to-Digital Converter Based on a Nonuniform Quantizer for a Photoplethysmographic Heart-Rate Sensor. 271-288 - Jaehyuk Choi, Seokjun Park, Jihyun Cho, Euisik Yoon:
A 3.4-µW Object-Adaptive CMOS Image Sensor With Embedded Feature Extraction Algorithm for Motion-Triggered Object-of-Interest Imaging. 289-300 - Leo Huf Campos Braga, Leonardo Gasparini, Lindsay Grant, Robert K. Henderson, Nicola Massari, Matteo Perenzoni, David Stoppa, Richard Walker:
A Fully Digital 8 × 16 SiPM Array for PET Applications With Per-Pixel TDCs and Real-Time Energy Output. 301-314 - Cristiano Niclass, Mineki Soga, Hiroyuki Matsubara, Masaru Ogawa, Manabu Kagami:
A 0.18-µm CMOS SoC for a 100-m-Range 10-Frame/s 200 × 96-Pixel Time-of-Flight Depth Sensor. 315-330
Volume 49, Number 2, February 2014
- Giuseppe Papotto, Francesco Carrara, Alessandro Finocchiaro, Giuseppe Palmisano:
A 90-nm CMOS 5-Mbps Crystal-Less RF-Powered Transceiver for Wireless Sensor Network Nodes. 335-346 - Xiang Yi, Chirn Chye Boon, Hang Liu, Jia-fu Lin, Wei Meng Lim:
A 57.9-to-68.3 GHz 24.6 mW Frequency Synthesizer With In-Phase Injection-Coupled QVCO in 65 nm CMOS Technology. 347-359 - Ahmad Mirzaei, Hooman Darabi:
Mutual Pulling Between Two Oscillators. 360-372 - Akshay Visweswaran, Robert Bogdan Staszewski, John R. Long:
A Low Phase Noise Oscillator Principled on Transformer-Coupled Hard Limiting. 373-383 - Aliakbar Homayoun, Behzad Razavi:
Relation Between Delay Line Phase Noise and Ring Oscillator Phase Noise. 384-391 - John G. Kauffman, Pascal Witte, Matthias Lehmann, Joachim Becker, Yiannos Manoli, Maurits Ortmanns:
A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW. 392-404 - Hyungil Chae, Jaehun Jeong, Gabriele Manganaro, Michael P. Flynn:
A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF. 405-415 - Yuichi Miyahara, Mitsuhiro Sano, Kazuo Koyama, Toshikazu Suzuki, Koichi Hamashita, Bang-Sup Song:
A 14b 60 MS/s Pipelined ADC Adaptively Cancelling Opamp Gain and Nonlinearity. 416-425 - Daibashish Gangopadhyay, Emily G. Allstot, Anna M. R. Dixon, Karthik Natarajan, Subhanshu Gupta, David J. Allstot:
Compressed Sensing Analog Front-End for Bio-Sensor Applications. 426-438 - Amir Borna, Khalil Najafi:
A Low Power Light Weight Wireless Multichannel Microsystem for Reliable Neural Recording. 439-451 - Ahmed Awny, Lothar Moeller, Joseph Junio, Christoph Scheytt, Andreas Thiede:
Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer. 452-470 - Takashi Takemoto, Hiroki Yamashita, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Yong Lee, Shinji Tsuji, Shinji Nishimura:
A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion. 471-485 - Chang-Joon Park, Marvin Onabajo, José Silva-Martínez:
External Capacitor-Less Low Drop-Out Regulator With 25 dB Superior Power Supply Rejection in the 0.4-4 MHz Range. 486-501 - Tae-Hwang Kong, Sung-Wan Hong, Gyu-Hyeong Cho:
A 0.791 mm2 On-Chip Self-Aligned Comparator Controller for Boost DC-DC Converter Using Switching Noise Robust Charge-Pump. 502-512 - Yingzhe Hu, Warren Rieutort-Louis, Josue Sanz-Robinson, Liechao Huang, Branko Glisic, James C. Sturm, Sigurd Wagner, Naveen Verma:
Large-Scale Sensing System Combining Large-Area Electronics and CMOS ICs for Structural-Health Monitoring. 513-523 - Daniele Raiteri, Pieter van Lieshout, Arthur H. M. van Roermund, Eugenio Cantatore:
Positive-Feedback Level Shifter Logic for Large-Area Electronics. 524-535 - Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai:
Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits. 536-544 - Kyle Craig, Yousef Shakhsheer, Saad Arrabi, Sudhanshu Khanna, John C. Lach, Benton H. Calhoun:
A 32 b 90 nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation From Sub-Threshold to High Performance. 545-552
Volume 49, Number 3, March 2014
- Michael P. Flynn:
New Associate Editor. 563 - Zheng Wang, Pei-Yuan Chiang, Peyman Nazari, Chun-Cheng Wang, Zhiming Chen, Payam Heydari:
A CMOS 210-GHz Fundamental Transceiver With OOK Modulation. 564-580 - Baradwaj Vigraham, Peter R. Kinget:
A Self-Duty-Cycled and Synchronized UWB Pulse-Radio Receiver SoC With Automatic Threshold-Recovery Based Demodulation. 581-594 - Saqib Subhan, Eric A. M. Klumperink, Amir Ghaffari, Gerard J. M. Wienk, Bram Nauta:
A 100-800 MHz 8-Path Polyphase Transmitter With Mixer Duty-Cycle Control Achieving <-40 dBc for ALL Harmonics. 595-607 - Youngchang Yoon, Hyoungsoo Kim, Hyungwook Kim, Kun-Seok Lee, Chang-Ho Lee, James S. Kenney:
A 2.4-GHz CMOS Power Amplifier With an Integrated Antenna Impedance Mismatch Correction System. 608-621 - Mark Stoopman, Shady Keyrouz, Hubregt J. Visser, Kathleen Philips, Wouter A. Serdijn:
Co-Design of a CMOS Rectifier and Small Loop Antenna for Highly Sensitive RF Energy Harvesters. 622-634 - Marco Garampazzi, Stefano Dal Toso, Antonio Liscidini, Danilo Manstretta, P. Mendez, Luca Romanò, Rinaldo Castello:
An Intuitive Analysis of Phase Noise Fundamental Limits Suitable for Benchmarking LC Oscillators. 635-645 - Antonio Liscidini, Luca Fanori, Pietro Andreani, Rinaldo Castello:
A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers. 646-656 - Wooseok Kim, Jaejin Park, Hojin Park, Deog-Kyoon Jeong:
Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator. 657-672 - Takumi Danjo, Masato Yoshioka, Masayuki Isogai, Masanori Hoshino, Sanroku Tsukamoto:
A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS. 673-682 - Jayanth Kuppambatti, Peter R. Kinget:
Current Reference Pre-Charging Techniques for Low-Power Zero-Crossing Pipeline-SAR ADCs. 683-694 - Seung-Chul Lee, Yun Chiu:
A 15-MHz Bandwidth 1-0 MASH Σ Δ ADC With Nonlinear Memory Error Calibration Achieving 85-dBc SFDR. 695-707 - Wei-Te Lin, Hung-Yi Huang, Tai-Haur Kuo:
A 12-bit 40 nm DAC Achieving SFDR > 70 dB at 1.6 GS/s and IMD < -61dB at 2.8 GS/s With DEMDRZ Technique. 708-717 - Adrian Colli-Menchi, Joselyn Torres, Edgar Sánchez-Sinencio:
A Feed-Forward Power-Supply Noise Cancellation Technique for Single-Ended Class-D Audio Amplifiers. 718-728 - Jingxue Lu, Hyejeong Song, Ranjit Gharpurey:
A CMOS Class-D Line Driver Employing a Phase-Locked Loop Based PWM Generator. 729-739 - Wei-Chung Chen, Su-Yi Ping, Tzu-Chi Huang, Yu-Huei Lee, Ke-Horng Chen, Chin-Long Wey:
A Switchable Digital-Analog Low-Dropout Regulator for Analog Dynamic Voltage Scaling Technique. 740-750 - Nhan Tran, Shun Bai, Jiawei Yang, Hosung Chun, Omid Kavehei, Yuanyuan Yang, Vijay Muktamath, David C. Ng, Hamish Meffin, Mark E. Halpern, Efstratios Skafidas:
A Complete 256-Electrode Retinal Prosthesis Chip. 751-765 - Hyunsik Kim, Junhyeok Yang, Sang-Hui Park, Seung-Tak Ryu, Gyu-Hyeong Cho:
A 10-Bit Column-Driver IC With Parasitic-Insensitive Iterative Charge-Sharing Based Capacitor-String Interpolation for Mobile Active-Matrix LCDs. 766-782 - Youn Sung Park, David T. Blaauw, Dennis Sylvester, Zhengya Zhang:
Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM. 783-794
Volume 49, Number 4, April 2014
- Hideyuki Kabuo, Jeffrey C. Gealow:
Introduction to the Special Issue on the 2013 Symposium on VLSI Circuits. 799-800 - Shu-Yu Hsu, Yingchieh Ho, Po-Yao Chang, Chauchin Su, Chen-Yi Lee:
A 48.6-to-105.2 µW Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications. 801-811 - David Jacquet, Frederic Hasbani, Philippe Flatresse, Robin Wilson, Franck Arnaud, Giorgio Cesana, Thierry Di Gilio, Christophe Lecocq, Tanmoy Roy, Amit Chhabra, Chiranjeev Grover, Olivier Minez, Jacky Uginet, Guy Durieu, Cyril Adobati, Davide Casalotto, Frederic Nyer, Patrick Menut, Andreia Cathelin, Indavong Vongsavady, Philippe Magarshack:
A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization. 812-826 - Dajiang Zhou, Jinjia Zhou, Gang He, Satoshi Goto:
A 1.59 Gpixel/s Motion Estimation Processor With -211 to +211 Search Range for UHDTV Video Encoder. 827-837 - Yingzhe Hu, Liechao Huang, Warren Rieutort-Louis, Josue Sanz-Robinson, James C. Sturm, Sigurd Wagner, Naveen Verma:
A Self-Powered System for Large-Scale Strain Sensing by Combining CMOS ICs With Large-Area Electronics. 838-850 - Yu-Jie Huang, Te-Hsuen Tzeng, Tzu-Wei Lin, Che-Wei Huang, Pei-Wen Yen, Po-Hung Kuo, Chih-Ting Lin, Shey-Shi Lu:
A Self-Powered CMOS Reconfigurable Multi-Sensor SoC for Biomedical Applications. 851-866 - Ryan M. Field, Simeon Realov, Kenneth L. Shepard:
A 100 fps, Time-Correlated Single-Photon-Counting-Based Fluorescence-Lifetime Imager in 130 nm CMOS. 867-880 - Bardia Bozorgzadeh, Daniel P. Covey, Christopher D. Howard, Paul A. Garris, Pedram Mohseni:
A Neurochemical Pattern Generator SoC With Switched-Electrode Management for Single-Chip Electrical Stimulation and 9.3 µW, 78 pA rms , 400 V/s FSCV Sensing. 881-895 - Jing Li, Robert K. Montoye, Masatoshi Ishii, Leland Chang:
1 Mb 0.41 µm2 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing. 896-907 - Meng-Fan Chang, Chia-Chen Kuo, Shyh-Shyuan Sheu, Chorng-Jung Lin, Ya-Chin King, Frederick T. Chen, Tzu-Kun Ku, Ming-Jinn Tsai, Jui-Jen Wu, Yu-Der Chih:
Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme. 908-916 - Rinkle Jain, Bibiche M. Geuskens, Stephen T. Kim, Muhammad M. Khellah, Jaydeep Kulkarni, James W. Tschanz, Vivek De:
A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS. 917-927 - Karthik Kadirvel, John Carpenter, Phuong Huynh, John Michael Ross, Robert Shoemaker, Brian Lum-Shue-Chan:
A Stackable, 6-Cell, Li-Ion, Battery Management IC for Electric Vehicles With 13, 12-bit ΣΔ ADCs, Cell Balancing, and Direct-Connect Current-Mode Communications. 928-934 - Shiuh-Hua Wood Chiang, Hyuk Sun, Behzad Razavi:
A 10-Bit 800-MHz 19-mW CMOS ADC. 935-949 - Sachin Rao, Karthikeyan Reddy, Brian Young, Pavan Kumar Hanumolu:
A Deterministic Digital Background Calibration Technique for VCO-Based ADCs. 950-960 - Taehwan Oh, Hariprasath Venkatram, Un-Ku Moon:
A Time-Based Pipelined ADC Using Both Voltage and Time Domain Information. 961-971 - Ahmad Mirzaei, Mohyee Mikhemar, David Murphy, Hooman Darabi:
A 2 dB NF Receiver With 10 mA Battery Current Suitable for Coexistence Applications. 972-983 - Brian P. Ginsburg, Srinath Ramaswamy, Vijay Rentala, Eunyoung Seok, Swaminathan Sankaran, Baher Haroun:
A 160 GHz Pulsed Radar Transceiver in 65 nm CMOS. 984-995 - Serkan Sayilir, Wing-Fai Loke, Jangjoon Lee, Harry Diamond, Benjamin R. Epstein, David L. Rhodes, Byunghoo Jung:
A -90 dBm Sensitivity Wireless Transceiver Using VCO-PA-LNA-Switch-Modulator Co-Design for Low Power Insect-Based Wireless Sensor Networks. 996-1006 - KwangSeok Kim, Wonsik Yu, SeongHwan Cho:
A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register. 1007-1016 - Bongjin Kim, Weichao Xu, Chris H. Kim:
A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based Loop Filter. 1017-1026 - Mark A. Ferriss, Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Daniel J. Friedman:
A 28 GHz Hybrid PLL in 32 nm SOI CMOS. 1027-1035 - Guanghua Shu, Saurabh Saxena, Woo-Seok Choi, Mrunmay Talegaonkar, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu:
A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop. 1036-1047 - Masum Hossain, Farrukh Aquil, Pak Shing Chau, Brian Tsang, Phuong Le, Jason Wei, Teva Stone, Barry Daly, Chanh Tran, John C. Eble, Kurt Knorpp, Jared Zerbe:
A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface. 1048-1062 - Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Yu Hsu, Shu-Chun Yang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang, Saman Adham, Min-Jer Wang, William Wu Shen, Ashok Mehta:
A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application. 1063-1074
Volume 49, Number 5, May 2014
- Waleed Khalil:
Introduction to the Special Section on the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. 1079-1080 - Wanghua Wu, Robert Bogdan Staszewski, John R. Long:
A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS. 1081-1096 - Run Chen, Hossein Hashemi:
A 0.5-to-3 GHz Software-Defined Radio Receiver Using Discrete-Time RF Signal Processing. 1097-1111 - Dlovan H. Mahrof, Eric A. M. Klumperink, Zhiyu Ru, Mark S. Oude Alink, Bram Nauta:
Cancellation of OpAmp Virtual Ground Imperfections by a Negative Conductance Applied to Improve RF Receiver Linearity. 1112-1124 - Piljae Park, Sungdo Kim, Sungchul Woo, Cheonsoo Kim:
A Centimeter Resolution, 10 m Range CMOS Impulse Radio Radar for Human Motion Monitoring. 1125-1134 - Xiongchuan Huang, Pieter Harpe, Guido Dolmans, Harmke de Groot, John R. Long:
A 780-950 MHz, 64-146 µW Power-Scalable Synchronized-Switching OOK Receiver for Wireless Event-Driven Applications. 1135-1147 - Amir Agah, Jefy Alex Jayamon, Peter M. Asbeck, Lawrence E. Larson, James F. Buckwalter:
Multi-Drive Stacked-FET Power Amplifiers at 90 GHz in 45 nm SOI CMOS. 1148-1157 - Anna Moroni, Raffaella Genesi, Danilo Manstretta:
Analysis and Design of a 54 GHz Distributed "Hybrid" Wave Oscillator Array With Quadrature Outputs. 1158-1172 - Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx:
A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range. 1173-1183 - Amr Elshazly, Sachin Rao, Brian Young, Pavan Kumar Hanumolu:
A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators - Analysis, Design, and Measurement Techniques. 1184-1197 - Sedigheh Hashemi, Behzad Razavi:
Analysis of Metastability in Pipelined ADCs. 1198-1209 - Denis Guangyin Chen, Fang Tang, Man Kay Law, Amine Bermak:
A 12 pJ/Pixel Analog-to-Information Converter Based 816 × 640 Pixel CMOS Image Sensor. 1210-1222 - Hamed Mazhab-Jafari, Karim Abdelhalim, Leyla Soleymani, Edward H. Sargent, Shana O. Kelley, Roman Genov:
Nanostructured CMOS Wireless Ultra-Wideband Label-Free PCR-Free DNA Analysis SoC. 1223-1241 - Yi Zhang, Dongsheng Ma:
A Fast-Response Hybrid SIMO Power Converter with Adaptive Current Compensation and Minimized Cross-Regulation. 1242-1255 - Vratislav Michal:
Absolute Value, 1% Linear and Lossless Current-Sensing Circuit for the Step-Down DC-DC Converters With Integrated Power Stage. 1256-1270 - Dongsuk Jeon, Michael B. Henry, Yejoong Kim, Inhee Lee, Zhengya Zhang, David T. Blaauw, Dennis Sylvester:
An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS. 1271-1284
Volume 49, Number 6, June 2014
- Bum-Kyum Kim, Donggu Im, Jaeyoung Choi, Kwyro Lee:
A Highly Linear 1 GHz 1.3 dB NF CMOS Low-Noise Amplifier With Complementary Transconductance Linearization. 1286-1302 - Amir Ghaffari, Eric A. M. Klumperink, Frank E. van Vliet, Bram Nauta:
A 4-Element Phased-Array System With Simultaneous Spatial- and Frequency-Domain Filtering at the Antenna Inputs. 1303-1316 - Francis Caster, Leland Gilreath, Shiji Pan, Zheng Wang, Filippo Capolino, Payam Heydari:
Design and Analysis of a W-band 9-Element Imaging Array Receiver Using Spatial-Overlapping Super-Pixels in Silicon. 1317-1332 - Zhicheng Lin, Pui-In Mak, Rui Paulo Martins:
A 2.4 GHz ZigBee Receiver Exploiting an RF-to-BB-Current-Reuse Blixer + Hybrid Filter Topology in 65 nm CMOS. 1333-1344 - Lingli Xia, Jiao Cheng, Neil E. Glover, Patrick Chiang:
0.56 V, -20 dBm RF-Powered, Multi-Node Wireless Body Area Network System-on-a-Chip With Harvesting-Efficiency Tracking Loop. 1345-1355 - Nam-Sik Ryu, Seung Hyun Jang, Kwang Chun Lee, Yongchae Jeong:
CMOS Doherty Amplifier With Variable Balun Transformer and Adaptive Bias Control for Wireless LAN Application. 1356-1365