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Publication search results
found 139 matches
- 1990
- Miron Abramovici, David T. Miller, R. Henning:
Global cost functions for test generation. ITC 1990: 35-43 - Leslie Ackner, Mark R. Barber:
Frequency enhancement of digital VLSI test systems. ITC 1990: 444-451 - Ajit Agrawal, Debashis Bhattacharya:
CMP3F: a high speed fault simulator for the Connection Machine. ITC 1990: 410-416 - Sheldon B. Akers Jr., Sungju Park, Balakrishnan Krishnamurthy, Ashok Swaminathan:
Why is less information from logic simulation more useful in fault simulation? ITC 1990: 786-800 - Don R. Allen:
Failure probability algorithm for test systems to reduce false alarms. ITC 1990: 648-656 - Keith Baker, Bas Verhelst:
IDDQ testing because 'zero defects isn't enough': a Philips perspective. ITC 1990: 253-254 - Paul H. Bardell:
Analysis of cellular automata used as pseudorandom pattern generators. ITC 1990: 762-768 - Philip E. Bishop, Grady Giles, Sudarshan Iyengar, C. Thomas Glover, Wai-On Law:
Testability considerations in the design of the MC68340 Integrated Processor Unit. ITC 1990: 337-346 - Ram Bobba, B. Stevens:
Fast embedded A/D converter testing using the microcontroller's resources. ITC 1990: 598-604 - Luis A. Bonet, J. Ganger, Jim Girardeau, Carlos Greaves, M. Pendleton, David Yatim:
Test features of the MC145472 ISDN U-transceivers. ITC 1990: 68-79 - Melvin A. Breuer:
Obstacles and an approach towards concurrent engineering. ITC 1990: 260-261 - Ove Brynestad, Einar J. Aas, Anne E. Vallestad:
State transition graph analysis as a key to BIST fault coverage. ITC 1990: 537-543 - Phil Burlison:
Criteria for analyzing high frequency testing performance of VLSI automatic test equipment. ITC 1990: 452-461 - Paolo Camurati, Davide Medina, Paolo Prinetto, Matteo Sonza Reorda:
A diagnostic test pattern generation algorithm. ITC 1990: 52-58 - Grant L. Castrodale, Apostolos Dollas, William T. Krakow:
An interactive environment for the transparent logic simulation and testing of integrated circuits. ITC 1990: 394-403 - John C. Chan, Jacob A. Abraham:
A study of faulty signatures using a matrix formulation. ITC 1990: 553-561 - V. Chandramouli, Ravi K. Gulati, Ramaswami Dandapani, Deepak K. Goel:
Bridging faults and their implication to PLAs. ITC 1990: 852-859 - J. Morris Chang:
A study of the optimization of DC parametric tests. ITC 1990: 478-487 - Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen:
Single-fault fault collapsing analysis in sequential logic circuits. ITC 1990: 809-814 - Kwang-Ting Cheng, Jing-Yang Jou:
Functional test generation for finite state machines. ITC 1990: 162-168 - Wu-Tung Cheng, James L. Lewandowski, Eleanor Wu:
Diagnosis for wiring interconnects. ITC 1990: 565-571 - Vivek Chickermane, Janak H. Patel:
An optimization based approach to the partial scan design problem. ITC 1990: 377-386 - Chul J. Choi:
Scan based guided probe technology delivers Cyclone to the market. ITC 1990: 115-119 - David T. Crook:
A fourth generation analog incircuit program generator. ITC 1990: 605-612 - Dharam Vir Das, Sharad C. Seth, Paul T. Wagner, John C. Anderson, Vishwani D. Agrawal:
An experimental study on reject ratio prediction for VLSI circuits: Kokomo revisited. ITC 1990: 712-720 - Bulent I. Dervisoglu:
Towards a standard approach for controlling board-level test functions. ITC 1990: 582-590 - Srinivas Devadas, Kurt Keutzer:
Design of integrated circuits fully testable for delay-faults and multifaults. ITC 1990: 284-293 - Noel E. Donlin:
QML (qualified manufacturing line): a method of providing high quality integrated circuits. ITC 1990: 262-263 - Robert B. Elo:
An empirical relationship between test transparency and fault coverage. ITC 1990: 1006-1011 - Michiaki Emori, Takashi Aikyo, Yasuhide Machida, Jun-ichi Shikatani:
ASIC CAD system based on hierarchical design-for-testability. ITC 1990: 404-409
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