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Publication search results
found 175 matches
- 2016
- Anup Das, Geoff V. Merrett, Mirco Tribastone, Bashir M. Al-Hashimi:
Workload Change Point Detection for Runtime Thermal Management of Embedded Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(8): 1358-1371 (2016) - Mukesh Agrawal, Krishnendu Chakrabarty, Bill Eklow:
A Distributed, Reconfigurable, and Reusable BIST Infrastructure for Test and Diagnosis of 3-D-Stacked ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(2): 309-322 (2016) - Majid Ahadi, Sourajeet Roy:
Sparse Linear Regression (SPLINER) Approach for Efficient Multidimensional Uncertainty Quantification of High-Speed Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1640-1652 (2016) - Seyed Nematollah Adel Ahmadyan, Shobha Vasudevan:
Automated Transient Input Stimuli Generation for Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(5): 858-871 (2016) - Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, Taewhan Kim:
Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2068-2081 (2016) - Antara Ain, Antonio Anastasio Bruto da Costa, Pallab Dasgupta:
Feature Indented Assertions for Analog and Mixed-Signal Validation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(11): 1928-1941 (2016) - Mirela Alistar, Paul Pop, Jan Madsen:
Synthesis of Application-Specific Fault-Tolerant Digital Microfluidic Biochip Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(5): 764-777 (2016) - Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Majority-Inverter Graph: A New Paradigm for Logic Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(5): 806-819 (2016) - Abdulazim Amouri, Jochen Hepp, Mehdi Baradaran Tahoori:
Built-In Self-Heating Thermal Testing of FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1546-1556 (2016) - Hyung-Chan An, Hoeseok Yang, Soonhoi Ha:
A Formal Approach to Power Optimization in CPSs With Delay-Workload Dependence Awareness. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(5): 750-763 (2016) - Baris Arslan, Alex Orailoglu:
Power-Aware Delay Test Quality Optimization for Multiple Frequency Domains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(1): 141-154 (2016) - Baris Arslan, Alex Orailoglu:
Aggressive Test Cost Reductions Through Continuous Test Effectiveness Assessment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2093-2103 (2016) - Valeriy Balabanov, Shuo-Ren Lin, Jie-Hong R. Jiang:
Flexibility and Optimization of QBF Skolem-Herbrand Certificates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1557-1568 (2016) - Hadi Ahmadi Balef, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram:
All-Region Statistical Model for Delay Variation Based on Log-Skew-Normal Distribution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1503-1508 (2016) - Domenico Balsamo, Anup Das, Alex S. Weddell, Davide Brunelli, Bashir M. Al-Hashimi, Geoff V. Merrett, Luca Benini:
Graceful Performance Modulation for Power-Neutral Transient Computing Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(5): 738-749 (2016) - Domenico Balsamo, Alex S. Weddell, Anup Das, Alberto Rodriguez Arreola, Davide Brunelli, Bashir M. Al-Hashimi, Geoff V. Merrett, Luca Benini:
Hibernus++: A Self-Calibrating and Adaptive System for Transiently-Powered Embedded Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 1968-1980 (2016) - Chongxi Bao, Domenic Forte, Ankur Srivastava:
On Reverse Engineering-Based Hardware Trojan Detection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(1): 49-57 (2016) - Alberto A. Del Barrio, Jason Cong, Román Hermida:
A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(3): 419-432 (2016) - Abhishek Basak, Swarup Bhunia:
P-Val: Antifuse-Based Package-Level Defense Against Counterfeit ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(7): 1067-1078 (2016) - Francesco Beneventi, Andrea Bartolini, Pascal Vivet, Luca Benini:
Thermal Analysis and Interpolation Techniques for a Logic + WideIO Stacked DRAM Test Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(4): 623-636 (2016) - Pietro Buccella, Camillo Stefanucci, Hao Zou, Yasser Moursy, Ramy Iskander, Jean-Michel Sallese, Maher Kayal:
Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1489-1502 (2016) - Florin Burcea, Husni M. Habal, Helmut E. Graeb:
A New Chessboard Placement and Sizing Method for Capacitors in a Charge-Scaling DAC by Worst-Case Analysis of Nonlinearity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1397-1410 (2016) - Ermao Cai, Da-Cheng Juan, Siddharth Garg, Jinpyo Park, Diana Marculescu:
Learning-Based Power/Performance Optimization for Many-Core Systems With Extended-Range Voltage/Frequency Scaling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(8): 1318-1331 (2016) - Caio Araujo T. Campos, Abner Luis Panho Marciano, Omar P. Vilela Neto, Frank Sill Torres:
USE: A Universal, Scalable, and Efficient Clocking Scheme for QCA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(3): 513-517 (2016) - Ying Chen, Tan Nguyen, Yao Chen, Swathi T. Gurumani, Yun Liang, Kyle Rupnow, Jason Cong, Wen-mei W. Hwu, Deming Chen:
FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2032-2045 (2016) - Hai-Bao Chen, Sheldon X.-D. Tan, Xin Huang, Taeyoung Kim, Valeriy Sukharev:
Analytical Modeling and Characterization of Electromigration Effects for Multibranch Interconnect Trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(11): 1811-1824 (2016) - Xiaoming Chen, Lin Wang, Boxun Li, Yu Wang, Xin Li, Yongpan Liu, Huazhong Yang:
Modeling Random Telegraph Noise as a Randomness Source and its Application in True Random Number Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1435-1448 (2016) - Ping Chi, Wang-Chien Lee, Yuan Xie:
Adapting B+ -Tree for Emerging Nonvolatile Memory-Based Main Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1461-1474 (2016) - Hui-Ju Katherine Chiang, Chi-Yuan Liu, Jie-Hong R. Jiang, Yao-Wen Chang:
Simultaneous EUV Flare Variation Minimization and CMP Control by Coupling-Aware Dummification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(4): 598-610 (2016) - Angelo Ciccazzo, Gianni Di Pillo, Vittorio Latorre:
A SVM Surrogate Model-Based Method for Parametric Yield Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(7): 1224-1228 (2016)
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