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Publication search results
found 35 matches
- 1995
- Gerard A. Allan, Anthony J. Walton:
Hierarchical critical area extraction with the EYE tool. DFT 1995: 28-36 - Gerard A. Allan, Anthony J. Walton:
Critical area extraction of extra material soft faults. DFT 1995: 55-62 - Anna Antola, Luca Breveglieri:
A model for the evaluation of fault tolerance in the FERMI system. DFT 1995: 72-80 - M. Baxter, D. Muir:
Using defect density modelling to drive the optimisation of circuit layout, maximising yield. DFT 1995: 164-172 - Yves Blaquière, Gabriel Gagné, Yvon Savaria, Claude Évéquoz:
Cost analysis of a new algorithmic-based soft-error tolerant architecture. DFT 1995: 189-197 - Cristiana Bolchini, R. Montandon, Fabio Salice, Donatella Sciuto:
Self-checking FSMs based on a constant distance state encoding. DFT 1995: 269-277 - P. Brahic, Régis Leveugle, Gabriele Saucier:
Design of defect-tolerant scan chains for MCMs with an active substrate. DFT 1995: 252-260 - Igor Bubel, Wojciech Maly, Thomas Waas, Pranab K. Nag, Hans Hartmann, Doris Schmitt-Landsiedel, Susanne Griep:
AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layout. DFT 1995: 10-18 - Glenn H. Chapman, D. E. Bergen, K. Fang:
Wafer-scale integration defect avoidance tradeoffs between laser links and Omega network switching. DFT 1995: 37-45 - Xiao-Tao Chen, Wei-Kang Huang, Fabrizio Lombardi, Xiao Sun:
A row-based FPGA for single and multiple stuck-at fault detection. DFT 1995: 225-233 - Zhan Chen, Israel Koren:
Layer assignment for yield enhancement. DFT 1995: 173-180 - Luigi Dadda, Vincenzo Piuri:
Bit-modular defect/fault-tolerant convolvers. DFT 1995: 90-98 - Aurobindo Dasgupta, Ramesh Karri:
Switch level hot-carrier reliability enhancement of VLSI circuits. DFT 1995: 63-71 - Frederic Duvivier, M. Rivier:
Approximation of critical area of ICs with simple parameters extracted from the layout. DFT 1995: 1-9 - Guilang Feng, Sihai Xiao, Xiaofa Shi, T. R. N. Rao:
Constructions of the SbEC-DbED and DbEC codes, and their applications. DFT 1995: 278-286 - Manoj Franklin:
A study of time redundant fault tolerance techniques for superscalar processors. DFT 1995: 207-215 - Dinesh D. Gaitonde, D. M. H. Walker, Wojciech Maly:
Accurate yield estimation of circuits with redundancy. DFT 1995: 155-163 - Stephanie R. Goldberg, Shambhu J. Upadhyaya:
Utilizing spares in multichip modules for the dual function of fault coverage and fault diagnosis. DFT 1995: 234-242 - Neil Harrison:
Yield projection from defect monitors: the influence of gross defects [BiCMOS process]. DFT 1995: 146-154 - Yuang-Ming Hsu, Vincenzo Piuri, Earl E. Swartzlander Jr.:
Efficient time redundancy for error correcting inner-product units and convolvers. DFT 1995: 198-206 - Hannu H. Kari, Heikki Saikkonen, Sungsoo Kim, Fabrizio Lombardi:
Repair algorithms for mirrored disk systems. DFT 1995: 216-224 - Jai-Hoon Kim, Fabrizio Lombardi, Nitin H. Vaidya:
An improved approach to fault tolerant rank order filtering on a SIMD mesh processor. DFT 1995: 137-145 - Jien-Chung Lo:
Single fault masking logic designs with error correcting codes. DFT 1995: 296- - Cecilia Metra, Michele Favalli, Bruno Riccò:
Novel Berger code checker. DFT 1995: 287-295 - Pranab K. Nag, Wojciech Maly:
Hierarchical extraction of critical area for shorts in very large ICs. DFT 1995: 19-27 - Ragini Narasimhan, Daniel J. Rosenkrantz, S. S. Ravi:
Efficient algorithms for analyzing and synthesizing fault-tolerant datapaths. DFT 1995: 81-89 - Mariagiovanna Sami, Fausto Distante, Renato Stefanelli:
A Channel-Constrained Reconfiguration Approach for Processing Arrays. DFT 1995: 99-107 - Adit D. Singh:
ADTS: an array defect-tolerance scheme for wafer scale gate arrays. DFT 1995: 126-136 - Itsuo Takanami, Tadayoshi Horita:
Reconfigurable architectures for mesh-arrays with PE and link faults. DFT 1995: 108-116 - Claude Thibeault, A. Payeur:
FFT-based test of a yield monitor circuit. DFT 1995: 243-251
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retrieved on 2024-04-26 18:54 CEST from data curated by the dblp team
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