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Publication search results
found 236 matches
- 2001
- Nazmy Abaskharoun, Mohamed M. Hafed, Gordon W. Roberts:
Strategies for on-chip sub-nanosecond signal capture and timing measurements. ISCAS (4) 2001: 174-177 - Mostafa I. H. Abd-El-Barr, C. Sundarram, A. S. Almulhem:
VLSI considerations in the design of k-ary n-cube interconnection networks. ISCAS (4) 2001: 278-281 - Adiseno, Mohammed Ismail, Håkan K. Olsson:
Dual-loop cross-coupled feedback amplifier for low-IF integrated receiver architecture. ISCAS (4) 2001: 470-473 - Rui L. Aguiar, Dinis M. Santos:
Oscillatorless clock multiplication. ISCAS (4) 2001: 630-633 - Edgar F. M. Albuquerque, Manuel M. Silva:
Evaluation of substrate noise in CMOS and low-noise logic cells. ISCAS (4) 2001: 750-753 - Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo:
CML ring oscillators: oscillation frequency. ISCAS (4) 2001: 112-115 - Pietro Andreani:
A 1.8-GHz monolithic CMOS VCO tuned by an inductive varactor. ISCAS (4) 2001: 714-717 - Li-Minn Ang, Hon Nin Cheung:
Hardware implementation of the depth first search bit stream SPIHT system. ISCAS (4) 2001: 518-521 - Wael M. Badawy, Magdy A. Bayoumi:
A mesh based motion tracking architecture. ISCAS (4) 2001: 262-265 - Yann Bajot, Habib Mehrez:
Customizable DSP architecture for ASIP core design. ISCAS (4) 2001: 302-305 - Viv A. Bartlett, Andrew G. Dempster:
Using carry-save adders in low-power multiplier blocks. ISCAS (4) 2001: 222-225 - Akil E. Bashagha:
Novel radix-2k division algorithm. ISCAS (4) 2001: 318-321 - Rolf Becker:
Control loop for optimization of power consumption in VLSI designs. ISCAS (4) 2001: 602-605 - Håkan Bengtson, Christer Svensson:
3V CMOS 0.35 µ transimpedance receiver for optical applications. ISCAS (4) 2001: 69-71 - Yngvar Berg, Snorre Aunet, Øivind Næss, Mats Høvin:
Exploiting sinh and tanh shaped ultra low-voltage floating-gate transconductance amplifiers to reduce harmonic distortion. ISCAS (4) 2001: 838-841 - Rachid Bouchakour, Nadia Harabech, Pierre Canet, Philippe Boivin, Jean Michel Mirable:
Modeling of a floating-gate EEPROM cell using a charge sheet approach including variable tunneling capacitance and polysilicon gate depletion effect. ISCAS (4) 2001: 822-825 - Ian Brynjolfson, Zeljko Zilic:
A new PLL design for clock management applications. ISCAS (4) 2001: 814-817 - Roberto Canegallo, Davide Dozza, Roberto Guerrieri:
Low power techniques for flash memories. ISCAS (4) 2001: 494-497 - Pierre Canet, Rachid Bouchakour, Nadia Harabech, Philippe Boivin, Jean-Michel Mirabel:
EEPROM programming study-time and degradation aspects. ISCAS (4) 2001: 846-849 - Ediz Çetin, Izzet Kale, Richard C. S. Morling:
Adaptive compensation of analog front-end I/Q mismatches in digital receivers. ISCAS (4) 2001: 370-373 - Alan N. L. Chan, Chun Bing Guo, Howard C. Luong:
A 1-V 2.4-GHz CMOS LNA with source degeneration as image-rejection notch filter. ISCAS (4) 2001: 890-893 - Alan N. L. Chan, Kenneth W. H. Ng, Joseph M. C. Wong, Howard C. Luong:
A 1-V 2.4-GHz CMOS RF receiver front-end for Bluetooth application. ISCAS (4) 2001: 454-457 - Wei-Hsin Chang, Yew-San Lee, Wen-Shiaw Peng, Chen-Yi Lee:
A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme. ISCAS (4) 2001: 330-333 - Ching-Chi Chang, Chien-Chih Lin, Muh-Tian Shiue, Chorng-Kuang Wang:
A wide pull-in range fast acquisition hardware-sharing two-fold carrier recovery loop. ISCAS (4) 2001: 358-361 - Yuyu Chang, Jack Wills, John Choma Jr.:
On-chip automatic direct tuning circuitry based on the synchronous rectification scheme for CMOS gigahertz band front-end filters. ISCAS (4) 2001: 246-249 - Cheng-Chih Chang, Ro-Min Weng, J. C. Huang, Kang Hsu, Kun-Yi Lin:
A 1.5 V high gain CMOS mixer for 2.4-GHz applications. ISCAS (4) 2001: 782-785 - Li-Hsun Chen, Oscal T.-C. Chen:
A low-complexity and high-speed Booth-algorithm FIR architecture. ISCAS (4) 2001: 338-341 - Kuan-Hung Chen, Shi-Chung Chang, Tzi-Dar Chiueh, Peter B. Luh, Xing Zhao:
SIMD architecture for job shop scheduling problem solving. ISCAS (4) 2001: 530-533 - Huo-Hsing Cheng, Ven-Chieh Hsieh:
A new logic synthesis and optimization procedure. ISCAS (4) 2001: 182-185 - Kuo-Hsing Cheng, Wei-Bin Yang, Chun-Fu Chung:
A low-power high driving ability voltage control oscillator used in PLL. ISCAS (4) 2001: 614-617
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