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ORCIDHLDVT 2000: Berkeley, California, USA
- Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, Berkeley, California, USA, November 8-10, 2000. IEEE Computer Society 2000, ISBN 0-7695-0786-7
Advances in High-Level Test I
- Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda
, Giovanni Squillero:
An RT-level fault model with high gate level correlation. 3-8 - Vivekananda M. Vedula, Jacob A. Abraham:
A novel methodology for hierarchical test generation using functional constraint composition. 9-14 - Christophe Paoli, Marie-Laure Nivet, Jean François Santucci:
Use of constraint solving in order to generate test vectors for behavioral validation. 15-20 - Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno:
Behavioral-level test vector generation for system-on-chip designs. 21-26
Validation and Test for Microprocessor Designs
- M. Beardo, Francesco Bruschi, Fabrizio Ferrandi, Donatella Sciuto:
An approach to functional testing of VLIW architectures. 29-33 - Matthias Pflanz, Christian Galke, Heinrich Theodor Vierhaus:
A new method for on-line state machine observation for embedded microprocessors. 34-39 - Hiroyuki Tomiyama, Taisei Yoshino, Nikil D. Dutt:
Verification of in-order execution in pipelined processors. 40-44
Hardware/Software Co-Validation
- Bart Vermeulen, Gert-Jan van Rootselaar:
Silicon debug of a co-processor array for video applications. 47-52 - Debashis Panigrahi, Clark N. Taylor, Sujit Dey:
Interface based hardware/software validation of a system-on-chip. 53-58 - Karen A. Tomko, Anurag Tiwari:
Hardware/software co-debugging for reconfigurable computing. 59-63 - Robert Pasko, Radim Cmar, Patrick Schaumont, Serge Vernalde:
Functional verification of an embedded network component by co-simulation with a real network. 64-67
Formal Verification Techniques and Applications
- M. S. Jahanpour, Eduard Cerny:
Compositional verification of an ATM switch module using interface recognizer/suppliers (IRS). 71-76 - Hoon Choi, Byeong-Whee Yun, Yun-Tae Lee:
Simulation strategy after model checking: experience in industrial SOC design. 77-79 - Rajesh Radhakrishnan, Elena Teica, Ranga Vemuri:
An approach to high-level synthesis system validation using formally verified transformations. 80-85
Issues in High-Level Design Validation
- Amjad Hajjar, Tom Chen, Anneliese von Mayrhauser:
On statistical behavior of branch coverage in testing behavioral VHDL models. 89-94 - Hajime Yamashita, Hiroto Yasuura, Eko Fajar, Yun Cao:
Variable size analysis and validation of computation quality. 95-100 - Stefan Koerner:
Code simulation concept for S/390 processors using an emulation system. 101-102
Advances in High-Level Test II
- Sandhya Seshadri, Michael S. Hsiao:
Formal operator testability methods for behavioral-level DFT using value ranges. 105-111 - Tianjing Jiang, Robert H. Klenke, James H. Aylor, Gang Han:
System level testability analysis using Petri nets. 112-117 - Dominique Federici, Paul Bisgambiglia, Jean François Santucci:
High level fault simulation: experiments and results on ITC'99 benchmarks. 118-123 - Anneliese von Mayrhauser, Tom Chen, Jan Kok, Chuck Anderson, Anita Read, Amjad Hajjar:
On choosing test criteria for behavioral level hardware design verification. 124-130
Formal Verification Techniques
- Yee-Wing Hsieh, Steven P. Levitan:
Abstraction techniques for verification of multiple tightly coupled counters, registers and comparators. 133-138 - Harry Hsieh, Felice Balarin:
Refining abstract equivalence analysis for embedded system design. 139-146 - Michael D. Jones, Ganesh Gopalakrishnan:
Toward automated abstraction for protocols on branching networks. 147-152
Advances in Simulation-Based Verification
- Fabian Wolf, Rolf Ernst:
Data flow based cache prediction using local simulation. 155-160 - Jürgen Ruf, Dirk W. Hoffmann, Thomas Kropf, Wolfgang Rosenstiel:
Checking temporal properties under simulation of executable system descriptions. 161-166 - Mihai T. Lazarescu, Jwahar R. Bammi, Edwin A. Harcourt, Luciano Lavagno, Marcello Lajolo:
Compilation-based software performance estimation for system level design. 167-172 - Cordula Hansen, Wolfgang Rosenstiel:
Transformation of algorithmic simulation vector sets considering mapping problems of I/O operations. 173-178
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