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ORCIDMEMSYS 2018: Alexandria, VA, USA
- Bruce L. Jacob:
Proceedings of the International Symposium on Memory Systems, MEMSYS 2018, Old Town Alexandria, VA, USA, October 01-04, 2018. ACM 2018, ISBN 978-1-4503-6475-1
Datacenters and large memories
- Dmitrii Ustiugov, Alexandros Daglis, Javier Picorel, Mark Sutherland, Edouard Bugnion, Babak Falsafi, Dionisios N. Pnevmatikatos
:
Design guidelines for high-performance SCM hierarchies. 3-16 - Hosein Mohammadi Makrani, Hossein Sayadi, Sai Manoj Pudukotai Dinakarrao, Setareh Rafatirad, Houman Homayoun:
A comprehensive memory analysis of data intensive workloads on server class architecture. 19-30 - Jingyuan Hu, Xiaokuang Bai, Sai Sha, Yingwei Luo, Xiaolin Wang, Zhenlin Wang:
HUB: hugepage ballooning in kernel-based virtual machines. 31-37 - Xiaoming Du, Cong Li:
Memory failure prediction using online learning. 38-49 - William Wang, Stephan Diestelhorst:
Quantify the performance overheads of PMDK. 50-52
Memory for parallel systems & architectures I
- Byoungchan Oh, Nam Sung Kim, Jeongseob Ahn, Bingchao Li, Ronald G. Dreslinski, Trevor N. Mudge:
A load balancing technique for memory channels. 55-66 - Mohammad Reza Jokar, Lunkai Zhang, Frederic T. Chong:
Cooperative NV-NUMA: prolonging non-volatile memory lifetime through bandwidth sharing. 67-78 - Gushu Li, Guohao Dai, Shuangchen Li, Yu Wang, Yuan Xie:
GraphIA: an in-situ accelerator for large-scale graph processing. 79-84 - Berkin Akin, Chiachen Chou, Jongsoo Park, Christopher J. Hughes, Rajat Agarwal:
Dynamic fine-grained sparse memory accesses. 85-97 - Meenatchi Jagasivamani, Candace Walden, Devesh Singh, Luyi Kang, Shang Li, Mehdi Asnaashari, Sylvain Dubois, Bruce L. Jacob, Donald Yeung:
Memory-systems challenges in realizing monolithic computers. 98-104
DRAM issues and architectures
- Rommel Sánchez Verdejo, Kazi Asifuzzaman, Milan Radulovic, Petar Radojkovic, Eduard Ayguadé, Bruce L. Jacob:
Main memory latency simulation: the missing link. 107-116 - Chao Yan, Russ Joseph:
Cocoa: synergistic cache compression and error correction in capacity sensitive last level caches. 117-128 - Alaa R. Alameldeen, Rajat Agarwal:
Opportunistic compression for direct-mapped DRAM caches. 129-136 - Sriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney, Thomas M. Conte, Hong Wang:
Tackling memory access latency through DRAM row management. 137-147 - Kira Kraft, Deepak M. Mathew, Chirag Sudarshan, Matthias Jung, Christian Weis, Norbert Wehn, Florian Longnos:
Efficient coding scheme for DDR4 memory subsystems. 148-157
Memory for parallel systems & architectures II
- James Alexander Edwards, Uzi Vishkin:
Linking parallel algorithmic thinking to many-core memory systems and speedups for boosted decision trees. 161-168 - Hugo Brunie, Julien Jaeger, Patrick Carribault, Denis Barthou:
Profile-guided scope-based data allocation method. 169-182 - High-level synthesis for irregular applications: enabling temporally multithreaded accelerators. 183-184
- Edgar A. León, Matthieu Hautreux:
Achieving transparency mapping parallel applications: a memory hierarchy affair. 185-189 - Ellis Giles, Kshitij A. Doshi, Peter J. Varman:
Hardware transactional persistent memory. 190-205
Modeling and simulation
- Zhiyuan Yang, Michael Zuzak, Ankur Srivastava:
HMCTherm: a cycle-accurate HMC simulator integrated with detailed power and thermal simulation. 209-117 - G. Scott Lloyd, Maya B. Gokhale:
Design space exploration of near memory accelerators. 218-220 - Zhizhou Zhang, Chencheng Ye, Rahman Lavaee, Ning Gu, Chen Ding:
Fine-grained data usage analysis by access sampling: seeing the data that is not there. 221-231 - Hao Luo, Guoyang Chen, Fangzhou Liu, Pengcheng Li, Chen Ding, Xipeng Shen:
Footprint modeling of cache associativity and granularity. 232-242 - Svetozar Miucin, Alexandra Fedorova:
Data-driven spatial locality. 243-253
Exotic technologies and applications
- Erik F. Anderson, Jorge González, Alexander Gazman, Rodolfo Azevedo, Keren Bergman:
Optically connected and reconfigurable GPU architecture for optimized peer-to-peer access. 257-258 - Tobias Lieske, Mehrdad Biglari, Dietmar Fey:
Multi-level memristive voltage divider: programming scheme trade-offs. 259-268 - Sebastian Werner, Pouya Fotouhi, Roberto Proietti, S. J. Ben Yoo:
AWGR-based optical processor-to-memory communication for low-latency, low-energy vault accesses. 269-278 - Hengyu Zhao, Jishen Zhao:
Leveraging MLC STT-RAM for energy-efficient CNN training. 279-290 - Antara Ganguly, Virendra Singh, Rajeev Muralidhar, Masahiro Fujita:
Memory-system requirements for convolutional neural networks. 291-197
Invited papers
- Yehia Arafa, Abdel-Hameed A. Badawy, Gopinath Chennupati, Nandakishore Santhi, Stephan J. Eidenbenz:
PPT-GPU: performance prediction toolkit for GPUs identifying the impact of caches: extended abstract. 301-302 - Anastasiia Butko, Albert Chen, David Donofrio, Farzad Fatollahi-Fard, John Shalf:
Open2C: open-source generator for exploration of coherent cache memory subsystems. 311-317 - Dane Brown, T. Owens Walker, Ryan N. Rakvic, Robert W. Ives, Hau T. Ngo, James Shey, Justin A. Blanco:
Towards detection of modified firmware on solid state drives via side channel analysis. 315-320 - Randall Burnett, Ryan Clarke, Timothy Lee, Harold Hearne, Jacob Vogel, Quentin Herr, Anna Herr:
Demonstration of superconducting memory for an RQL CPU. 321-323
Experimentations & optimizations
- Frederick A. Ware, Javier Bueno, Liji Gopalakrishnan, Brent Haukness, Chris Haywood, Toni Juan, Eric Linstadt, Sally A. McKee, Steven C. Woo, Kenneth L. Wright, Craig Hampel, Gary Bronner:
Architecting a hardware-managed hybrid DIMM optimized for cost/performance. 327-340 - Shang Li, Dhiraj Reddy, Bruce L. Jacob:
A performance & power comparison of modern high-speed DRAM architectures. 341-353 - Pascal Francis-Mezger, Vincent M. Weaver:
A raspberry pi operating system for exploring advanced memory system concepts. 354-364 - John D. Leidel:
Stake: a coupled simulation environment for RISC-V memory experiments. 365-376 - Matthias Jung, Sally A. McKee, Chirag Sudarshan, Christoph Dropmann, Christian Weis, Norbert Wehn:
Driving into the memory wall: the role of memory for advanced driver assistance systems and autonomous driving. 377-386
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