"Tackling memory access latency through DRAM row management."

Sriseshan Srikanth et al. (2018)

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DOI: 10.1145/3240302.3240314

access: closed

type: Conference or Workshop Paper

metadata version: 2024-10-06

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Sriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney, Thomas M. Conte, Hong Wang:
Tackling memory access latency through DRAM row management. MEMSYS 2018: 137-147

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