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ORCID21st ASYNC 2015: Mountain View, CA, USA
- 21st IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2015, Mountain View, CA, USA, May 4-6, 2015. IEEE Computer Society 2015, ISBN 978-1-4799-8716-0
Session 1: Crossing Clock Boundaries
- Ben Keller, Matthew Fojtik, Brucek Khailany:
A Pausible Bisynchronous FIFO for GALS Systems. 1-8 - Robert Najvirt, Andreas Steininger
:
How to Synchronize a Pausible Clock to a Reference. 9-16 - Louis-Charles Trudeau, Ghyslain Gagnon, François Gagnon, Claude Thibeault, Thomas Awad, Doug Morrissey:
A Low-Latency, Energy-Efficient L1 Cache Based on a Self-Timed Pipeline. 17-18 - Jerome Cox, George Engel, David M. Zar, Ian W. Jones:
Synchronizers and Data Flip-Flops are Different. 19-20
Session 2: Circuit Design and Case Studies
- Dylan Hand, Matheus Trevisan Moreira, Hsin-Ho Huang, Danlei Chen, Frederico Butzke, Zhichao Li, Matheus Gibiluka, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel:
Blade - A Timing Violation Resilient Asynchronous Template. 21-28 - Danil Sokolov, Victor Khomenko, Andrey Mokhov, Alex Yakovlev, David Lloyd:
Design and Verification of Speed-Independent Multiphase Buck Controller. 29-36 - Sean Keller, Alain J. Martin, Chris Moore:
DD1: A QDI, Radiation-Hard-by-Design, Near-Threshold 18uW/MIPS Microcontroller in 40nm Bulk CMOS. 37-44
Session 3: Demos
Session 4: Physical Design and Optimization
- Robert Karmazin, Stephen Longfield Jr., Carlos Tadeo Ortega Otero, Rajit Manohar:
Timing Driven Placement for Quasi Delay-Insensitive Circuits. 45-52 - Gang Wu, Ankur Sharma, Chris C. N. Chu:
Gate Sizing and Vth Assignment for Asynchronous Circuits Using Lagrangian Relaxation. 53-60 - Dylan Hand, Hsin-Ho Huang, Benmao Cheng, Yang Zhang, Matheus Trevisan Moreira, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel:
Performance Optimization and Analysis of Blade Designs under Delay Variability. 61-68
Session 5: New Perspectives
- Rajit Manohar, Yoram Moses:
Analyzing Isochronic Forks with Potential Causality. 69-76 - Marly Roncken, Swetha Mettala Gilla, Hoon Park, Navaneeth Jamadagni, Chris Cowan, Ivan E. Sutherland:
Naturalized Communication and Testing. 77-84
Session 6: Cryptoprocessors and NOCs
- Carlos Tadeo Ortega Otero, Jonathan Tse, Rajit Manohar:
AES Hardware-Software Co-design in WSN. 85-92 - Neela Lohith Penmetsa, Christos P. Sotiriou, Sung Kyu Lim:
Low Power Monolithic 3D IC Design of Asynchronous AES Core. 93-99 - Guangda Zhang, Jim D. Garside, Wei Song, Javier Navaridas, Zhiying Wang:
Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults. 100-107
Session 7: Fresh Ideas
Session 8: Merge, Mutual Exclusion, and Arbitration
- Gabriele Miorandi, Davide Bertozzi, Steven M. Nowick:
Increasing Impartiality and Robustness in High-Performance N-Way Asynchronous Arbiters. 108-115 - Andrey Mokhov, Victor Khomenko, Danil Sokolov, Alex Yakovlev:
Opportunistic Merge Element. 116-123 - Yang Zhang, Leandro S. Heck, Matheus T. Moreira, David Zar, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel:
Design and Analysis of Testable Mutual Exclusion Elements. 124-131
Session 9: Emerging Technologies
- Jiaoyan Chen, Arnaud Tisserand, Emanuel M. Popovici, Sorin Cotofana:
Asynchronous Charge Sharing Power Consistent Montgomery Multiplier. 132-138 - Eldar Zianbetov, Edith Beigné, Gregory di Pendina:
Non-volatility for Ultra-Low Power Asynchronous Circuits in Hybrid CMOS/Magnetic Technology. 139-146
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