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ORCID22nd ASYNC 2016: Porto Alegre, Brazil
- 22nd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2016, Porto Alegre, Brazil, May 8-11, 2016. IEEE Computer Society 2016, ISBN 978-1-4673-9007-1
Session 1: Clocking, Delay Lines and Margins
- Suwen Yang, Frankie Y. Liu, Vincent C. Lee:
Asynchronously Controlled Frequency Locked Loop. 3-10 - Ramy N. Tadros, Weizhe Hua, Matheus Gibiluka, Matheus T. Moreira, Ney Laert Vilar Calazans
, Peter A. Beerel:
Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications. 11-18 - Jordi Cortadella, Marc Lupon, Alberto Moreno, Antoni Roca, Sachin S. Sapatnekar:
Ring Oscillator Clocks and Margins. 19-26
Session 2: Faults, Fault Avoidance and Resiliency
- Sandra J. Jackson, Rajit Manohar:
Gradual Synchronization. 29-36 - Felipe A. Kuentzer, Alexandre M. Amory:
Fault Classification of the Error Detection Logic in the Blade Resilient Template. 37-42 - Dylan Hand, Austin Katrin, William Koven:
Adding Conditionality to Resilient Bundled-Data Designs. 43-44 - Yan Peng, Ian W. Jones, Mark R. Greenstreet:
Finding Glitches Using Formal Methods. 45-46
Session 3: Metastability and Synchronization
- Christoph Lenzen, Moti Medina:
Efficient Metastability-Containing Gray Code 2-Sort. 49-56 - Andreas Steininger, Jürgen Maier, Robert Najvirt:
The Metastable Behavior of a Schmitt-Trigger. 57-64
Session 4: Noise Control, GALS Systems and Yield
- Milan Babic, Steffen Zeidler, Milos Krstic:
GALS Partitioning Methodology for Substrate Noise Reduction in Mixed-Signal Integrated Circuits. 67-74 - Divya Akella Kamakshi, Matthew Fojtik, Brucek Khailany, Sudhir S. Kudva, Yaping Zhou, Benton H. Calhoun:
Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive Clocks. 75-82 - Mahdi Jelodari Mamaghani, Milos Krstic, Jim D. Garside:
Automatic Clock: A Promising Approach toward GALSification. 83-84
Session 5: Asynchronous Applications and Security
- Benjamin Z. Tang, Frank Lane:
Low Power QDI Asynchronous FFT. 87-88
Session 6: New Methods for Asynchronous Controllers
- Jotham Vaddaboina Manoranjan, Kenneth S. Stevens:
Qualifying Relative Timing Constraints for Asynchronous Circuits. 91-98 - Norman Kluge, Ralf Wollowski:
Optimising Bundled-Data Balsa Circuits. 99-106 - Javier de San Pedro, Thomas Bourgeat, Jordi Cortadella:
Specification Mining for Asynchronous Controllers. 107-114
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