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ORCID11th FMCAD 2011: Austin, TX, USA
- Per Bjesse, Anna Slobodová:
International Conference on Formal Methods in Computer-Aided Design, FMCAD '11, Austin, TX, USA, October 30 - November 02, 2011. FMCAD Inc. 2011, ISBN 978-0-9835678-1-3 - Aarti Gupta
:
Verifying concurrent programs: tutorial talk. 1 - Ivan E. Sutherland:
Self-timing: a step beyond synchrony (tutorial talk). 2 - Fabio Somenzi, Aaron R. Bradley:
IC3: where monolithic and incremental meet. 3-8 - Prashant Aggarwal, Darrow Chu, Vijay Kadamby, Vigyan Singhal:
Planning for end-to-end formal using simulation-based coverage: invited tutorial. 9-16 - John Hughes:
Specification based testing with QuickCheck: tutorial talk. 17 - J Strother Moore:
The role of human creativity in mechanized verification: invited talk. 18 - Kenneth L. McMillan:
Interpolants from Z3 proofs. 19-27 - Alberto Griggio:
Effective word-level interpolation for software verification. 28-36 - Anton Belov, João Marques-Silva:
Accelerating MUS extraction with recursive model rotation. 37-40 - Panagiotis Manolios, Vasilis Papavasileiou:
Pseudo-Boolean Solving by incremental translation to SAT. 41-45 - Harsh Raju Chamarthi, Panagiotis Manolios:
Automated specification analysis using an interactive theorem prover. 46-53 - Alessandro Cimatti, Sergio Mover, Stefano Tonetta:
Proving and explaining the unfeasibility of message sequence charts for hybrid systems. 54-62 - Charlie Shucheng Zhu, Georg Weissenbacher, Sharad Malik:
Post-silicon fault localisation using maximum satisfiability and backbones. 63-66 - Mohamed Abdul Basith, Tariq B. Ahmad, André Rossi, Maciej J. Ciesielski:
Algebraic approach to arithmetic design verification. 67-71 - Sagar Chaki, Arie Gurfinkel, Ofer Strichman:
Time-bounded analysis of real-time systems. 72-80 - Jonathan Kotker, Dorsa Sadigh, Sanjit A. Seshia:
Timing analysis of interrupt-driven programs under context bounds. 81-90 - Robert Könighofer, Roderick Bloem:
Automated error localization and correction for imperative programs. 91-100 - Michael L. Case, Jason Baumgartner, Hari Mony, Robert Kanzelman:
Optimal redundancy removal without fixedpoint computation. 101-108 - Michael L. Case, Jason Baumgartner, Hari Mony, Robert Kanzelman:
Approximate reachability with combined symbolic and ternary simulation. 109-115 - Bryan A. Brady, Randal E. Bryant, Sanjit A. Seshia:
Learning conditional abstractions. 116-124 - Niklas Eén, Alan Mishchenko, Robert K. Brayton:
Efficient implementation of property directed reachability. 125-134 - Hana Chockler, Alexander Ivrii, Arie Matsliah, Shiri Moran, Ziv Nevo:
Incremental formal verification of hardware. 135-143 - Aaron R. Bradley, Fabio Somenzi, Zyad Hassan, Yan Zhang:
An incremental approach to model checking progress properties. 144-153 - Muralidhar Talupur:
Hardware model checking: status, challenges, and opportunities. 154 - John Havlicek, Scott Little:
Realtime regular expressions for analog and mixed-signal assertions. 155-162 - Umair Siddique, Osman Hasan:
Formal analysis of fractional order systems in HOL. 163-170 - Louis Mandel, Florence Plateau, Marc Pouzet:
Static scheduling of latency insensitive designs with Lucy-n. 171-175 - Steven M. German:
A theory of abstraction for arrays. 176-185 - Brad D. Bingham, Mark R. Greenstreet, Jesse D. Bingham:
Parameterized verification of deadlock freedom in symmetric cache coherence protocols. 186-195 - Jayanand Asok Kumar, Lingyi Liu, Shobha Vasudevan:
Scaling probabilistic timing verification of hardware using abstractions in design source code. 196-205 - Lee Pike:
Pervasive formal verification in control system design. 206 - Jun Sawada, Peter Sandon, Viresh Paruthi, Jason Baumgartner, Michael L. Case, Hari Mony:
Hybrid verification of a hardware modular reduction engine. 207-214 - Sudarshan K. Srinivasan, Raj S. Katti:
Desynchronization: design for verification. 215-222 - Freek Verbeek, Julien Schmaltz:
Hunting deadlocks efficiently in microarchitectural models of communication fabrics. 223-231
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