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2020 – today
- 2023
[j64]Qi Nie
, Sharad Malik:
CNNFlow: Memory-driven Data Flow Optimization for Convolutional Neural Networks. ACM Trans. Design Autom. Electr. Syst. 28(3): 40:1-40:36 (2023)- [c194]Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, Sharad Malik:
INVITED: Generalizing the ISA to the ILA: A Software/Hardware Interface for Accelerator-rich Platforms. DAC 2023: 1-4 - [i6]Qinhan Tan, Yonathan Fisseha, Shibo Chen, Lauren Biernacki, Jean-Baptiste Jeannin, Sharad Malik, Todd M. Austin:
Security Verification of Low-Trust Architectures. CoRR abs/2309.00181 (2023) - 2022
- [c193]Yue Xing, Aarti Gupta, Sharad Malik:
Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models. ASP-DAC 2022: 154-159 - [c192]Yu Zeng, Aarti Gupta, Sharad Malik:
Automatic Generation of Architecture-Level Models from RTL Designs for Processors and Accelerators. DATE 2022: 460-465 - [c191]Yue Xing, Huaixi Lu, Aarti Gupta, Sharad Malik:
Compositional Verification Using a Formal Component and Interface Specification. ICCAD 2022: 72:1-72:9 - [c190]Qinhan Tan, Aarti Gupta, Sharad Malik:
Usage-Based RTL Subsetting for Hardware Accelerators. ICCAD 2022: 73:1-73:9 - [i5]Bo-Yuan Huang, Steven Lyubomirsky, Yi Li, Mike He, Thierry Tambe, Gus Henry Smith, Akash Gaonkar, Vishal Canumalla, Gu-Yeon Wei, Aarti Gupta, Zachary Tatlock, Sharad Malik:
Specialized Accelerators and Compiler Flows: Replacing Accelerator APIs with a Formal Software/Hardware Interface. CoRR abs/2203.00218 (2022) - 2021
- [j63]Lauren Biernacki, Mark Gallagher, Zhixing Xu, Misiker Tadesse Aga, Austin Harris, Shijia Wei, Mohit Tiwari, Baris Kasikci, Sharad Malik, Todd M. Austin:
Software-driven Security Attacks: From Vulnerability Sources to Durable Hardware Defenses. ACM J. Emerg. Technol. Comput. Syst. 17(3): 42:1-42:38 (2021) - [c189]Yue Xing, Huaixi Lu, Aarti Gupta, Sharad Malik:
Leveraging Processor Modeling and Verification for General Hardware Modules. DATE 2021: 1130-1135 - [c188]Yu Zeng, Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, Sharad Malik:
Generating Architecture-Level Abstractions from RTL Designs for Processors and Accelerators Part I: Determining Architectural State Variables. ICCAD 2021: 1-9 - [c187]Hongce Zhang, Aarti Gupta, Sharad Malik:
Syntax-Guided Synthesis for Lemma Generation in Hardware Model Checking. VMCAI 2021: 325-349 - [p10]João Marques-Silva, Inês Lynce, Sharad Malik:
Conflict-Driven Clause Learning SAT Solvers. Handbook of Satisfiability 2021: 133-182 - 2020
- [j62]Qi Nie, Sharad Malik:
MemFlow: Memory-Driven Data Scheduling With Datapath Co-Design in Accelerators for Large-Scale Inference Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(9): 1875-1888 (2020) - [c186]Hongce Zhang, Weikun Yang, Grigory Fedyukovich, Aarti Gupta, Sharad Malik:
Synthesizing Environment Invariants for Modular Hardware Verification. VMCAI 2020: 202-225
2010 – 2019
- 2019
- [j61]Bo-Yuan Huang, Hongce Zhang, Pramod Subramanyan, Yakir Vizel, Aarti Gupta, Sharad Malik:
Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification. ACM Trans. Design Autom. Electr. Syst. 24(1): 10:1-10:24 (2019) - [j60]Burçin Çakir, Sharad Malik:
Revealing Cluster Hierarchy in Gate-level ICs Using Block Diagrams and Cluster Estimates of Circuit Embeddings. ACM Trans. Design Autom. Electr. Syst. 24(5): 50:1-50:19 (2019) - [c185]Sharad Malik, Pareesa Ameneh Golnari:
Sparse Matrix to Matrix Multiplication: A Representation and Architecture for Acceleration. ASAP 2019: 67-70 - [c184]Mark Gallagher, Lauren Biernacki, Shibo Chen, Zelalem Birhanu Aweke, Salessawi Ferede Yitbarek, Misiker Tadesse Aga, Austin Harris, Zhixing Xu, Baris Kasikci, Valeria Bertacco, Sharad Malik, Mohit Tiwari, Todd M. Austin:
Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defenses with Churn. ASPLOS 2019: 469-484 - [c183]Qi Nie, Sharad Malik:
SpFlow: Memory-Driven Data Flow Optimization for Sparse Matrix-Matrix Multiplication. ISCAS 2019: 1-5 - [c182]Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, Sharad Malik:
ILAng: A Modeling and Verification Platform for SoCs Using Instruction-Level Abstractions. TACAS (1) 2019: 351-357 - [i4]Pareesa Ameneh Golnari, Sharad Malik:
Sparse Matrix to Matrix Multiplication: A Representation and Architecture for Acceleration (long version). CoRR abs/1906.00327 (2019) - 2018
- [j59]Pramod Subramanyan, Bo-Yuan Huang, Yakir Vizel, Aarti Gupta, Sharad Malik:
Template-Based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(8): 1692-1705 (2018) - [j58]Burçin Çakir, Sharad Malik:
Reverse Engineering Digital ICs through Geometric Embedding of Circuit Graphs. ACM Trans. Design Autom. Electr. Syst. 23(4): 50:1-50:19 (2018) - [c181]Qi Nie, Sharad Malik:
MemFlow: Memory-driven data scheduling with datapath co-design in accelerators for large-scale inference applications. ASP-DAC 2018: 446-451 - [c180]Weikun Yang, Yakir Vizel, Pramod Subramanyan, Aarti Gupta, Sharad Malik:
Lazy Self-composition for Security Verification. CAV (2) 2018: 136-156 - [c179]Bo-Yuan Huang, Sayak Ray, Aarti Gupta, Jason M. Fung, Sharad Malik:
Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware. DAC 2018: 91:1-91:6 - [c178]Hongce Zhang, Caroline Trippel, Yatin A. Manerkar, Aarti Gupta, Margaret Martonosi, Sharad Malik:
ILA-MCM: Integrating Memory Consistency Models with Instruction-Level Abstractions for Heterogeneous System-on-Chip Verification. FMCAD 2018: 1-10 - [c177]Todd M. Austin, Valeria Bertacco, Baris Kasikci, Sharad Malik, Mohit Tiwari:
Vulnerability-tolerant secure architectures. ICCAD 2018: 46 - [c176]Yue Xing, Bo-Yuan Huang, Aarti Gupta, Sharad Malik:
A formal instruction-level GPU model for scalable verification. ICCAD 2018: 130 - [p9]João Marques-Silva, Sharad Malik:
Propositional SAT Solving. Handbook of Model Checking 2018: 247-275 - [i3]Bo-Yuan Huang, Hongce Zhang, Pramod Subramanyan, Yakir Vizel, Aarti Gupta, Sharad Malik:
Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification. CoRR abs/1801.01114 (2018) - 2017
- [j57]Pareesa Ameneh Golnari, Yavuz Yetim, Margaret Martonosi, Yakir Vizel, Sharad Malik:
PPU: A Control Error-Tolerant Processor for Streaming Applications with Formal Guarantees. ACM J. Emerg. Technol. Comput. Syst. 13(3): 43:1-43:29 (2017) - [c175]Zhixing Xu, Sayak Ray, Pramod Subramanyan, Sharad Malik:
Malware detection using machine learning based analysis of virtual memory access patterns. DATE 2017: 169-174 - [c174]Pareesa Ameneh Golnari, Sharad Malik:
Evaluating matrix representations for error-tolerant computing. DATE 2017: 1659-1662 - [c173]Yakir Vizel, Alexander Nadel, Sharad Malik:
Solving linear arithmetic with SAT-based model checking. FMCAD 2017: 47-54 - [c172]Zhixing Xu, Aarti Gupta, Sharad Malik:
Trace-based Analysis of Memory Corruption Malware Attacks. Haifa Verification Conference 2017: 67-82 - [c171]Yakir Vizel, Alexander Nadel, Sharad Malik:
Solving Constraints over Bit-Vectors with SAT-based Model Checking. SMT 2017: 101-107 - [c170]Yakir Vizel, Arie Gurfinkel, Sharon Shoham, Sharad Malik:
IC3 - Flipping the E in ICE. VMCAI 2017: 521-538 - 2016
- [j56]Alexander Ivrii, Sharad Malik, Kuldeep S. Meel, Moshe Y. Vardi:
On computing minimal independent support and its applications to sampling and counting. Constraints An Int. J. 21(1): 41-58 (2016) - [j55]Divjyot Sethi, Muralidhar Talupur, Sharad Malik:
Model checking unbounded concurrent lists. Int. J. Softw. Tools Technol. Transf. 18(4): 375-391 (2016) - [c169]Kuldeep S. Meel, Moshe Y. Vardi, Supratik Chakraborty, Daniel J. Fremont, Sanjit A. Seshia, Dror Fried, Alexander Ivrii, Sharad Malik:
Constrained Sampling and Counting: Universal Hashing Meets SAT Solving. AAAI Workshop: Beyond NP 2016 - [c168]Sharad Malik, Pramod Subramanyan:
Invited - Specification and modeling for systems-on-chip security verification. DAC 2016: 66:1-66:6 - [c167]Pramod Subramanyan, Sharad Malik, Hareesh Khattri, Abhranil Maiti, Jason M. Fung:
Verifying information flow properties of firmware using symbolic execution. DATE 2016: 337-342 - 2015
- [j54]Yakir Vizel, Georg Weissenbacher, Sharad Malik:
Boolean Satisfiability Solvers and Their Applications in Model Checking. Proc. IEEE 103(11): 2021-2035 (2015) - [c166]Yavuz Yetim, Sharad Malik, Margaret Martonosi:
CommGuard: Mitigating Communication Errors in Error-Prone Parallel Execution. ASPLOS 2015: 311-323 - [c165]Yakir Vizel, Arie Gurfinkel, Sharad Malik:
Fast Interpolating BMC. CAV (1) 2015: 641-657 - [c164]Sunha Ahn, Sharad Malik, Aarti Gupta:
Completeness bounds and sequentialization for model checking of interacting firmware and hardware. CODES+ISSS 2015: 202-211 - [c163]Burçin Çakir, Sharad Malik:
Hardware Trojan detection for gate-level ICs using signal correlation based clustering. DATE 2015: 471-476 - [c162]Charlie Shucheng Zhu, Sharad Malik:
Optimizing dynamic trace signal selection using machine learning and linear programming. DATE 2015: 1289-1292 - [c161]Sharad Malik:
Detecting Hardware Trojans: A Tale of Two Techniques. FMCAD 2015: 6 - [c160]Pramod Subramanyan, Yakir Vizel, Sayak Ray, Sharad Malik:
Template-based Synthesis of Instruction-Level Abstractions for SoC Verification. FMCAD 2015: 160-167 - [c159]Pramod Subramanyan, Sayak Ray, Sharad Malik:
Evaluating the security of logic encryption algorithms. HOST 2015: 137-143 - [c158]Ameneh Golnari, Yakir Vizel, Sharad Malik:
Error-Tolerant Processors: Formal Specification and Verification. ICCAD 2015: 286-293 - [i2]Kuldeep S. Meel, Moshe Y. Vardi, Supratik Chakraborty, Daniel J. Fremont, Sanjit A. Seshia, Dror Fried, Alexander Ivrii, Sharad Malik:
Constrained Sampling and Counting: Universal Hashing Meets SAT Solving. CoRR abs/1512.06633 (2015) - 2014
- [j53]Pramod Subramanyan, Nestan Tsiskaridze, Wenchao Li, Adrià Gascón, Wei Yang Tan, Ashish Tiwari, Natarajan Shankar, Sanjit A. Seshia, Sharad Malik:
Reverse Engineering Digital Circuits Using Structural and Functional Analyses. IEEE Trans. Emerg. Top. Comput. 2(1): 63-80 (2014) - [c157]Divjyot Sethi, Muralidhar Talupur, Sharad Malik:
Using Flow Specifications of Parameterized Cache Coherence Protocols for Verifying Deadlock Freedom. ATVA 2014: 330-347 - [c156]Sunha Ahn, Sharad Malik:
Automated firmware testing using firmware-hardware interaction patterns. CODES+ISSS 2014: 25:1-25:10 - [c155]Shuyuan Zhang, Franjo Ivancic, Cristian Lumezanu, Yifei Yuan, Aarti Gupta, Sharad Malik:
An Adaptable Rule Placement for Software-Defined Networks. DSN 2014: 88-99 - [c154]Adrià Gascón, Pramod Subramanyan, Bruno Dutertre, Ashish Tiwari, Dejan Jovanovic, Sharad Malik:
Template-based circuit understanding. FMCAD 2014: 83-90 - [c153]Roderick Bloem, Sharad Malik, Matthias Schlaipfer, Georg Weissenbacher:
Reduction of Resolution Refutations and Interpolants via Subsumption. Haifa Verification Conference 2014: 188-203 - [c152]Charlie Shucheng Zhu, Georg Weissenbacher, Sharad Malik:
Silicon fault diagnosis using sequence interpolation with backbones. ICCAD 2014: 348-355 - [c151]Shuyuan Zhang, Sharad Malik, Sanjai Narain, Laurent Vanbever:
In-Band Update for Network Routing Policy Migration. ICNP 2014: 356-361 - [c150]Sayak Ray, Sharad Malik:
Effective abstraction for response proof of communication fabrics. NOCS 2014: 188-189 - [c149]Ryan Beckett, Xuan Kelvin Zou, Shuyuan Zhang, Sharad Malik, Jennifer Rexford, David Walker:
An assertion language for debugging SDN applications. HotSDN 2014: 91-96 - [c148]Yinlei Yu, Pramod Subramanyan, Nestan Tsiskaridze, Sharad Malik:
All-SAT Using Minimal Blocking Clauses. VLSID 2014: 86-91 - [p8]Georg Weissenbacher, Pramod Subramanyan, Sharad Malik:
Boolean Satisfiability: Solvers and Extensions. Software Systems Safety 2014: 223-278 - [i1]Divjyot Sethi, Muralidhar Talupur, Sharad Malik:
Using Flow Specifications of Parameterized Cache Coherence Protocols for Verifying Deadlock Freedom. CoRR abs/1407.7468 (2014) - 2013
- [c147]Shuyuan Zhang, Sharad Malik:
SAT Based Verification of Network Data Planes. ATVA 2013: 496-505 - [c146]Yavuz Yetim, Margaret Martonosi, Sharad Malik:
Extracting useful computation from error-prone processors for streaming applications. DATE 2013: 202-207 - [c145]Pramod Subramanyan, Nestan Tsiskaridze, Kanika Pasricha, Dillon Reisman, Adriana Susnea, Sharad Malik:
Reverse engineering digital circuits using functional analysis. DATE 2013: 1277-1280 - [c144]Divjyot Sethi, Srinivas Narayana, Sharad Malik:
Abstractions for model checking SDN controllers. FMCAD 2013: 145-148 - [c143]Wenchao Li, Adrià Gascón, Pramod Subramanyan, Wei Yang Tan, Ashish Tiwari, Sharad Malik, Natarajan Shankar, Sanjit A. Seshia:
WordRev: Finding word-level structures in a sea of bit-level gates. HOST 2013: 67-74 - [c142]Sunha Ahn, Sharad Malik:
Modeling Firmware as Service Functions and Its Application to Test Generation. Haifa Verification Conference 2013: 61-77 - [c141]Divjyot Sethi, Muralidhar Talupur, Sharad Malik:
Model Checking Unbounded Concurrent Lists. SPIN 2013: 320-340 - 2012
- [c140]Yavuz Yetim, Sharad Malik, Margaret Martonosi:
EPROF: An energy/performance/reliability optimization framework for streaming applications. ASP-DAC 2012: 769-774 - [c139]Shuyuan Zhang, Sharad Malik, Rick McGeer:
Verification of Computer Switching Networks: An Overview. ATVA 2012: 1-16 - [c138]Daniel Schwartz-Narbonne, Georg Weissenbacher, Sharad Malik:
Parallel Assertions for Architectures with Weak Memory Models. ATVA 2012: 254-268 - [c137]Daniel Schwartz-Narbonne, Feng Liu, David I. August, Sharad Malik:
passert: A Tool for Debugging Parallel Programs. CAV 2012: 751-757 - [c136]Carven Chan, Daniel Schwartz-Narbonne, Divjyot Sethi, Sharad Malik:
Specification and synthesis of hardware checkpointing and rollback mechanisms. DAC 2012: 1226-1232 - [c135]Arnab Sinha, Sharad Malik, Aarti Gupta:
Efficient predictive analysis for detecting nondeterminism in multi-threaded programs. FMCAD 2012: 6-15 - [c134]Charlie Shucheng Zhu, Georg Weissenbacher, Sharad Malik:
Coverage-Based Trace Signal Selection for Fault Localisation in Post-silicon Validation. Haifa Verification Conference 2012: 132-147 - [c133]Shuyuan Zhang, Abdulrahman Mahmoud, Sharad Malik, Sanjai Narain:
Verification and synthesis of firewalls using SAT and QBF. ICNP 2012: 1-6 - [c132]Divjyot Sethi, Muralidhar Talupur, Daniel Schwartz-Narbonne, Sharad Malik:
Parameterized Model Checking of Fine Grained Concurrency. SPIN 2012: 208-226 - [c131]Georg Weissenbacher, Daniel Kroening, Sharad Malik:
Wolverine: Battling Bugs with Interpolants - (Competition Contribution). TACAS 2012: 556-558 - [p7]Georg Weissenbacher, Sharad Malik:
Boolean Satisfiability Solvers: Techniques and Extensions. Software Safety and Security 2012: 205-253 - 2011
- [j52]Divjyot Sethi, Yogesh S. Mahajan, Sharad Malik:
Specification and encoding of transaction interaction properties. Formal Methods Syst. Des. 39(2): 144-164 (2011) - [c130]Charlie Shucheng Zhu, Georg Weissenbacher, Sharad Malik:
Post-silicon fault localisation using maximum satisfiability and backbones. FMCAD 2011: 63-66 - [c129]Charlie Shucheng Zhu, Georg Weissenbacher, Divjyot Sethi, Sharad Malik:
SAT-based techniques for determining backbones for post-silicon fault localisation. HLDVT 2011: 84-91 - [c128]Arnab Sinha, Sharad Malik, Chao Wang, Aarti Gupta:
Predicting Serializability Violations: SMT-Based Search vs. DPOR-Based Search. Haifa Verification Conference 2011: 95-114 - [c127]Arnab Sinha, Sharad Malik, Chao Wang, Aarti Gupta:
Predictive analysis for detecting serializability violations through Trace Segmentation. MEMOCODE 2011: 99-108 - [c126]Daniel Schwartz-Narbonne, Feng Liu, Tarun Pondicherry, David I. August, Sharad Malik:
Parallel assertions for debugging parallel programs. MEMOCODE 2011: 181-190 - [c125]Sharad Malik:
Runtime Verification: A Computer Architecture Perspective. RV 2011: 49-62 - [c124]Sanjai Narain, Sharad Malik, Ehab Al-Shaer:
Towards Eliminating Configuration Errors in Cyber Infrastructure. SafeConfig 2011 - 2010
- [c123]Yogesh S. Mahajan, Sharad Malik:
Utility of transaction-level hardware models in refinement checking. HLDVT 2010: 121-128 - [c122]Arnab Sinha, Sharad Malik:
Runtime checking of serializability in software transactional memory. IPDPS 2010: 1-12
2000 – 2009
- 2009
- [j51]Sharad Malik, Lintao Zhang:
Boolean satisfiability from theoretical hardness to practical success. Commun. ACM 52(8): 76-82 (2009) - [j50]Aarti Gupta, Sharad Malik:
Preface. Formal Methods Syst. Des. 35(1): 1 (2009) - [c121]Daniel Schwartz-Narbonne, Carven Chan, Yogesh S. Mahajan, Sharad Malik:
Supporting RTL flow compatibility in a microarchitecture-level design framework. CODES+ISSS 2009: 343-352 - [p6]João Marques-Silva, Inês Lynce, Sharad Malik:
Conflict-Driven Clause Learning SAT Solvers. Handbook of Satisfiability 2009: 131-153 - 2008
- [j49]Jan M. Rabaey, Sharad Malik:
Challenges and Solutions for Late- and Post-Silicon Design. IEEE Des. Test Comput. 25(4): 296-302 (2008) - [j48]Sanjai Narain, Gary Levin, Sharad Malik, Vikram Kaul:
Declarative Infrastructure Configuration Synthesis and Debugging. J. Netw. Syst. Manag. 16(3): 235-258 (2008) - [c120]Kaiyu Chen, Sharad Malik, Priyadarsan Patra:
Runtime validation of memory ordering using constraint graph checking. HPCA 2008: 415-426 - [c119]Kaiyu Chen, Sharad Malik, Priyadarsan Patra:
Runtime Validation of Transactional Memory Systems. ISQED 2008: 750-756 - [c118]Sharad Malik:
Hardware Verification: Techniques, Methodology and Solutions. TACAS 2008: 1 - [c117]Yinlei Yu, Cameron Brien, Sharad Malik:
Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers. VLSI Design 2008: 461-468 - [e2]Aarti Gupta, Sharad Malik:
Computer Aided Verification, 20th International Conference, CAV 2008, Princeton, NJ, USA, July 7-14, 2008, Proceedings. Lecture Notes in Computer Science 5123, Springer 2008, ISBN 978-3-540-70543-7 [contents] - 2007
- [j47]Xinping Zhu, Sharad Malik:
A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs. ACM Trans. Design Autom. Electr. Syst. 12(1): 6:1-6:24 (2007) - [c116]Yogesh S. Mahajan, Sharad Malik:
Automating Hazard Checking in Transaction-Level Microarchitecture Models. FMCAD 2007: 62-65 - [c115]Yogesh S. Mahajan, Carven Chan, Ali Alphan Bayazit, Sharad Malik, Wei Qin:
Verification Driven Formal Architecture and Microarchitecture Modeling. MEMOCODE 2007: 123-132 - [c114]Zhaohui Fu, Sharad Malik:
Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions. VLSI Design 2007: 37-42 - [p5]Wei Qin, Sharad Malik:
Architecture Description Languages for Retargetable Compilation. The Compiler Design Handbook, 2nd ed. 2007: 16 - [p4]Subramanian Rajagopalan, Sharad Malik:
A Retargetable Very Long Instruction Word Compiler Framework for Digital Signal Processors. The Compiler Design Handbook, 2nd ed. 2007: 18 - 2006
- [j46]Manish Vachharajani, Neil Vachharajani, David A. Penry, Jason A. Blome, Sharad Malik, David I. August:
The Liberty Simulation Environment: A deliberate approach to high-level system modeling. ACM Trans. Comput. Syst. 24(3): 211-249 (2006) - [j45]Xinping Zhu, Wei Qin, Sharad Malik:
Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation. IEEE Trans. Very Large Scale Integr. Syst. 14(7): 707-716 (2006) - [c113]Cameron Brien, Sharad Malik:
Understanding the Dynamic Behavior of Modern DPLL SAT Solvers through Visual Analysis. FMCAD 2006: 49-50 - [c112]Zhaohui Fu, Sharad Malik:
Solving the minimum-cost satisfiability problem using SAT based branch-and-bound search. ICCAD 2006: 852-859 - [c111]Kaiyu Chen, Sharad Malik:
Dependable Multithreaded Processing Using Runtime Validation. PRDC 2006: 275-286 - [c110]Yinlei Yu, Sharad Malik:
Lemma Learning in SMT on Linear Constraints. SAT 2006: 142-155 - [c109]Zhaohui Fu, Sharad Malik:
On Solving the Partial MAX-SAT Problem. SAT 2006: 252-265 - [c108]