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ORCIDIMW 2025: Monterey, CA, USA
- IEEE International Memory Workshop, IMW 2025, Monterey, CA, USA, May 18-21, 2025. IEEE 2025, ISBN 979-8-3503-6298-5
- Eknath Sarkar, Dyutimoy Chakraborty, Wei-Chun Wang, Khandker Akif Aabrar, Sharadindu Gopal Kirtania, Omkar Phadke, Chengyang Zhang, Emmanuel Quezada, Jaewon Shin, Shida Zhang, Asif Islam Khan, Shimeng Yu, Saibal Mukhopadhyay, Suman Datta:
Analog In-Memory-Compute with Multi-bit Silicon Ferro FinFET Array for Improved Energy and Area Efficiency. 1-4 - Song-Hyeon Kuk, Bong Ho Kim, Young-Keun Park, Hyeon-Seong Hwang, Jae-Hoon Han, Byung Jin Cho, Byung Chul Jang, Sang-Hyeon Kim:
Proposal of Block Erase and Verify Schemes for Ferroelectric NAND: Overcoming Critical Challenges from Threshold Voltage Polarity. 1-4 - Yu-Hsuan Lin, Po-Hao Tseng, Ming-Hsiu Lee, Yu-Yu Lin, Feng-Min Lee, Dai-Ying Lee, Pei-Ying Du, Chih-Chieh Lin, Teng-Hao Yeh, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu:
Utilizing 2T SONOS Cell Characteristics for L2/Euclidean Distance Computing - From Unit Cell to Array Operations. 1-4 - Koji Sakui, Daniele Garbin, Yoshihisa Iwata, Gautam Gaddemane, Yisuo Li, Yiqun Wan, Ken'ichi Kanazawa, Eyup Can Demir, Iwao Kunishima, Andrea Fantini, Masakazu Kakumu, Christophe Lorant, Nozomu Harada:
Dynamic Flash Memory Operation Experimentally Validated with 65nm SOI Technology. 1-4 - Jeongyoon Yeo, Joonsung Kim, Younghwan Son, Taein Lee, Sejun Park, Min-Kyu Jeong, Jung Hoon Lee, Suk-Kang Sung, Dongku Kang, Seungwan Hong, Sunghoi Hur:
Innovative V-NAND Flash Structure with Dual Trap Layer for Future Generations of Multi-Bit Device. 1-4 - E. Piccinini, N. Giuliani, Matteo Baldo, Elisa Petroni, S. Calvi, L. Laurin, F. Nardi, Andrea Redaelli, Roberto Annunziata, L. Larcher:
Simulation of Ge-rich PCM Device Material Evolution from Post-Deposition Anneal to Programming Operations. 1-4 - Joshua Collins, Sanjay Gopinath, Kaihan Ashtiani, Shruti Thombare, Xiaolan Ba, Griffin Kennedy, Juwen Gao:
Deposition of ALD-Molybdenum for Flash Memory Wordline Metallization. 1-4 - Chanyang Park, Min-Kyu Jeong, Taein Lee, Sejun Park, Jung Hoon Lee, Yujin Lee, Seungwan Hong, Sunghoi Hur:
First Demonstration of Threshold Voltage Modeling in Multi-Hole V-NAND Flash Architecture with Noncircular Channel Hole Profiles. 1-4 - John Hoang, George Matamis, Calvin Pham, Hao Chi, Jonathan Church, Pramod Subramonium:
Enabling Merged 3D NAND Memory Hole and Interlayer Dielectric (ILD) Contact Etches with Deposition and Etch Co-Optimization (DECO). 1-4 - Mufeng Chen, Luqi Zheng, Jian-Yu Lin, Peide D. Ye, Haitong Li:
Analog Multilevel eDRAM-RRAM CIM for Zeroth-Order Fine-tuning of LLMs. 1-4 - Masaaki Higuchi, Albert Fayrushin, Aurelio Giancarlo Mauri, Haitao Liu, Yoshiaki Fukuzumi:
Modeling of the impact of elliptical shapes on main Read Window Budget mechanisms in 3D NAND. 1-4 - T. V. A. Nguyen, H. Naganuma, H. Honjo, Y. Sato, T. Tanigawa, S. Ikeda, T. Endoh:
Low write power and Field-free sub-ns write speed SOT-MRAM cell with Design Technology of Canted SOT structure and Magnetic Anisotropy for NVM. 1-4 - Mor M. Dahan, Emanuel Ber, Florian Wunderwald, Gilad Zilberman, Guy Orlev, Yair Keller, Einav Raveh, Ruben Alcala, Thomas Mikolajick, Uwe Schroeder, Eilam Yalon:
Novel Ultrafast Non-Destructive Readout of FeRAM by Low-Voltage Transient Current. 1-4 - H. Tsai, Hadjer Benmeziane, Irem Boybat, Julian Büchel, P. Narayanan, Manuel Le Gallo, S. Jain, Athanasios Vasilopoulos, W. Simon, Kohji Hosokawa, M. Ishii, Yasuteru Kohda, A. Chen, Charles Mackin, Kaoutar El Maghraoui, Atsuya Okazaki, Alexander M. Friz, Jose Luquin, A. Sebastian, V. Narayanan, Geoffrey W. Burr:
Analog AI Accelerators for Transformer-based Language Models: Hardware, Workload, and Power Performance. 1-4 - Sai Sukruth Bezugam, Tinish Bhattacharya, Horst Petschenig, S. Choi, George Higgins Hutchinson, Giacomo Pedretti, X. Sheng, Jim Ignowski, Thomas Van Vaerenbergh, Raymond G. Beausoleil, Robert Legenstein, Dmitri B. Strukov:
Controlling ReRAM's Switching Characteristics with Shadow Memory for Continual Learning. 1-4 - Onur Mutlu, Ataberk Olgun, Ismail Emir Yüksel:
Memory-Centric Computing: Solving Computing's Memory Problem. 1-4 - Po-Kai Hsu, Sungwon Cho, Janak Sharda, Hyeonwoo Park, Suman Datta, Shimeng Yu:
Monolithic 3D Stackable DRAM Design with BEOL-Compatible Oxide Channel Access Transistor. 1-4 - C. L. Sung, D. Daudelin, Wei-Chih Chien, R. C. Jordan, S. Cheng, Lynne M. Gignac, Douglas M. Bishop, C. W. Yeh, L. Buzi, C. W. Cheng, J. X. Zheng, E. K. Lai, A. Ray, Alexander Grun, H. Y. Cheng, C. H. Lin, T. W. Chang, T. Takken, Robert L. Bruce, M. Bright Sky, H. L. Lung:
Enhancing 3D XPT/SOM Reliability: Strategies for Mitigating Spike Current and Improving Read Endurance. 1-4 - Abhijith Prakash, Xiang Yang, James Kai, Xiaochen Zhu, Henry Chin, Guirong Liang, Deepanshu Dutta, Masaaki Higashitani, Kazuki Isozumi, Shinsuke Yada, Sayako Nagamine, Kenichi Okabe, Yutaka Ohira, Manabu Hayashi, Satoshi Shimizu, Hideto Tomiie, Takayuki Inoue, Shota Murai, Takeshi Sakaguchi, Youichi Minemura, Shoichi Miyazaki, Megumi Ishiduki, Yasuhiro Shiino, Shinji Suzuki:
Low Cost 'On Pitch Select Gate' (OPS) Technology for 3D Flash Memory. 1-4 - Hiroshi Maejima, Katsuaki Isobe, N. Okada, Masaki Unno, T. Hashimoto, Tetsuaki Utsumi, T. Hisada, K. Maruyama, Toshiyuki Kouchi, T. Kotani, Hitoshi Shiga, O. Kwon, A. Ganguly, Y. Wu, Hiroki Yabe, I. Lu, F. Toyama, Naohito Morozumi, Masahito Takehara, Takuya Ariki, I. Yoon:
Crossed Bit Line (CBL) Architecture in 3D Flash Memory CMOS Directly Bonded to Array (CBA) Structure. 1-4 - Wooseok Choi, Thomas van Bodegraven, Jelle Verest, Olivier Maher, Donato Francesco Falcone, Antonio La Porta, Daniel Jubin, Bert J. Offrein, Siegfried F. Karg, Valeria Bragaglia, Aida Todri-Sanial:
Hardware Implementation of Ring Oscillator Networks Coupled by BEOL Integrated ReRAM for Associative Memory Tasks. 1-4 - S. Krishnan, Shyam Surthi, Martin Popp, Richard J. W. Hill, Fabio Pellizzer, Paolo Tessariol, Yoshiaki Fukuzumi:
NAND flash innovation in the AI Era. 1-4 - Hechen Ji, Lin Bao, Haisu Zhang, Qishen Wang, Yuhang Yang, Yingtong Ji, Ruiqing Xie, Jingwei Sun, Yingchen Ji, Hao Zhang, Zhenghao Zhai, Zongwei Wang, Yimao Cai, Shanguo Huang:
High-parallel In-memory Data Sorting based on 40nm Analog RRAM Chip. 1-4 - Su-Jin Ahn, Young Guen Song, Dongguk Cho, Daewon Ha, Wanki Kim, Kwangmin Park, Kwangjin Moon, Jin-Woo Han, Seon Il Shim, Sangjin Hyun, Jaihyuk Song:
Future Technology Outlook on DRAM/Flash Memories for More Moore and More Than Moore. 1-4 - Daisuke Matsubayashi, Subhali Subhechha, Hyungrock Oh, Nouredine Rassoul, Shamin Houshmand Sharifi, Yiqun Wan, Shreya Kundu, Harinarayanan Puliyalil, Harold Dekkers, Alexandru Pavel, Inhee Lee, Gouri Sankar Kar, Attilio Belmonte:
Accurate off-current evaluation by parasitic capacitance extraction in capacitor-less DRAM cells. 1-4 - Lance Fernandes, Prasanna Venkatesan Ravindran, Mengkun Tian, Yu-Hsin Kuo, Nashrah Afroze, Salma Soliman, Sanghyun Kang, Dyutimoy Chakraborty, Taeyoung Song, Chengyang Zhang, Kijoon Kim, Kwangyou Seo, Kwangsoo Kim, Wanki Kim, Daewon Ha, Shimeng Yu, Suman Datta, Asif Khan:
Comparative Study of Channel Materials for Ferroelectric NAND Applications. 1-4 - Taegon Lee, Ji-Eun Ha, Kang-In Lee, Jung-Hwan Lee, Hyung-Geun Yook, In-Chul Shin, Jang-Hwan Jeong, Minkyu Kang, Joonsung Lim, Kyungyoon Noh, Seungwan Hong, Sunghoi Hur:
On-Chip Capacitors with Wall-Type Structure in 9th Generation 3D VNAND Flash Memory. 1-4 - Teng-Hao Yeh, Hang-Ting Lue, Wei-Chen Chen, Keh-Chung Wang, Chih-Yuan Lu:
A Novel 3D Stacked Vertical-Channel High-Voltage Peripheral Transistor for Largely Scaled the WL Driver Circuit of 1000-layer 3D NAND Flash. 1-4 - Junyoung Lee, Minkyu Jeong, Sejun Park, Joonam Kim, Joonghyeob Shin, Jongyoon Choi, Jihoon Choi, Byungsoo Kim, Yujeong Seo, Gilsung Lee, Dongsik Lee, Joon Kim, Suk-Kang Sung, Byoungil Lee, Seungwan Hong, Sunghoi Hur:
Development of Innovative Self-Aligned SSL Mold (SASM) Scheme with Remarkable Reduction of Chip Size. 1-4 - Kana Kudo, Yuta Aiba, Kazuma Hasegawa, Xu Li, Yuichi Sano, Tomoya Sanuki:
Energy-Efficient In-Memory Computing using 3D Flash Memory with Sequential Multi-Block Activation and Current Control Cell (CC cell). 1-4 - Prasanna Venkatesan, Asif Khan:
Ferroelectrics for Vertical NAND Flash Applications. 1-4 - David Lehninger, Ayse Sünbül, Hannes Mähne, Thomas Kämpfe, Alison Viegas, Justine Barbot, Kerstin Bernert, Steffen Thiem, Konrad Seidel, Maximilian Lederer:
Al-Doped HZO: A BEoL compatible Ferroelectric Material for Automotive-Grade Memory. 1-4 - M. Correa Cueto, Bastien Giraud, M. Drouard, Giuseppe Piccolboni, Gabriel Molas, Gaël Pillonnet:
Relaxation-Aware Programming in RRAM: Evaluating and Optimizing Write Termination. 1-4 - P. H. Tseng, F. M. Lee, C. C. Yang, H. W. Chiang, C. T. Huang, Y. H. Lin, Yu-Yu Lin, N. C. Lin, P. J. Sung, C. T. Wu, W. F. Wu, C. H. Shen, T. H. Hou, A. Y. Wu, H. Y. Cheng, T. H. Yeh, M. H. Lee, K. Y. Hsieh:
Monolithic 3D Macro Integrating CMOS with Ambipolar SONOS Tunnel FET for High Performance Edge-AI Computing Applications. 1-4 - Djihad Nacereddine Bouakaz, Mohit Dandekar, Jelle Biesmans, Wim Dehaene, Kris Myny:
1kb IGZO TFT Based Flexible SRAM for IoT Applications. 1-4 - Syed M. Alam, X. Zhang, H. Xu, M. Sadd, M. DeHerrera, S. Ikegawa, Fred B. Mancoff, K. Nagel, Y. Kim, S. Aggarwal:
STT-MRAM Antifuse Macro for Memory, SoC, and FPGA Chips. 1-4 - Steven Lemke, Louisa Schneider, Zonglin Li, Nhan Do:
Reliability and Accuracy of a Qualified Split-Gate Flash In-Memory Compute Technology. 1-4 - Anurag Swarnkar, Dawit Burusie Abdi, Bhawana Kumari, Priya Venugopal, Nicolas Pantano, Geert Hellings, Jaydeep Kulkarni, Dwaipayan Biswas, Julien Ryckaert, Fernando García-Redondo:
Design Technology Co-Optimization of 3D SRAM Macro in Nanosheet Technology for High-Bandwidth Applications. 1-4 - Pufan Xu, Peng Yao, Bin Gao, Jianshi Tang, He Qian, Huaqiang Wu:
A Precision-Adaptive ECC Strategy with Computing Fusion Decoding for Near/In-Memory Computing. 1-4 - S. Rachidi, S. Ramesh, Devin Verreck, J. Loyo, Y. Jeong, H. Puliyalil, J. Li, F. Seidel, Geert Van Den Bosch, Maarten Rosmeulen:
Hole-Side Airgap Integration as Enabler for 3D NAND Flash Z-Pitch Scaling. 1-4 - Tarcisius Januel, Olivier Billoint, Laurent Grenouillet, S. Martin, Jean-Michel Portal, Elisa Vianello:
Dual-Mode 16kb Memory: Transforming a Ferroelectric Capacitor Bitcell into Resistive Filamentary Memory. 1-4 - Hao-Ling Tang, Keith T. Wong, Minrui Yu, Jason Appell, Pei Liu, Chunyu Wong, Yi-Hsuan Sharon Hsiao, Hongwen Zhou, Luc Thomas, Lixia Rong, Lavinia Nistor, Ming-Hui Chiu, Xin Meng, Jee-Jay Chen, Dongqing Yang, Gopal Bajaj, Arvind Kumar, Michel Frei, Srinivas D. Nemani, Mahendra Pakala, Ellie Yieh:
Demonstration of Conformal MoS2 on High-Aspect-Ratio Structures up to 40: 1 and Exploration of Manufacturability in a 300mm Fab for 3D NAND applications. 1-4 - Junnosuke Furukawa, Koki Shibata, Kenshin Yamauchi, Naoko Misawa, Satoshi Awamura, Chihiro Matsui, Ken Takeuchi:
Bayesian Neural Network Realization by Random Telegraph Noise in 40nm TaOX ReRAM CiM. 1-4 - Albert B. Chen, Dong-Il Moon, Zhenni Wan, Jiahui Yuan, Henry Chin, Changyuan Chen:
On the Challenges of Open-Block Reads in 3D NAND. 1-4
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last updated on 2025-06-27 18:20 CEST by the dblp team
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