default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIntegration, Volume 91
Volume 91, July 2023
- Shuo Cai
, Yan Wen, Caicai Xie, Weizheng Wang, Fei Yu:
Low-power and high-speed SRAM cells for double-node-upset recovery. 1-9 - Yipei Yang, Zongyue Wang, Jing Ye, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li, Yuan Cao:
Chosen ciphertext correlation power analysis on Kyber. 10-22 - Wen Chen, Lang Li, Ying Guo, Ying Huang:
SAND-2: An optimized implementation of lightweight block cipher. 23-34 - Efstratios Zacharelos, Italo Nunziata, Gerardo Saggese, Antonio G. M. Strollo, Ettore Napoli:
Approximate squaring circuits exploiting recursive architectures. 35-42 - Navnit Kumar, Manjeet Kumar, Neeta Pandey:
CCTA based four different pairs of mutually coupled circuit using single topology. 43-53 - Yuntao Liu, Shuo Fang, Lijing Wang, Yun Wang:
An ultra-low power dissipation CMOS temperature sensor with an inaccuracy of ±0.15 °C (3δ) from -40 °C to 125 °C. 54-59 - Jiahong Zhang, Zhuo Wang, Chao Ma:
A CMOS transimpedance amplifier with broad-band and high gain based on negative Miller capacitance. 60-66 - Shaohui Yan, Jianjian Wang, Ertong Wang, Qiyu Wang, Xi Sun, Lin Li:
A four-dimensional chaotic system with coexisting attractors and its backstepping control and synchronization. 67-78 - Bipasha Nath, Sheng-Yu Peng, Zu-Jia Lo, Yu-Hsuan Pai, Yi-Ting Yeh, Huang-Hsiang Chang, Yi-Ching Lu, Shu-Hui Huang, Fang-Chia Chang:
A biphasic current-mode stimulator integrated circuit with a novel residual charge compensation mechanism. 79-88 - P. Manikandan:
A feed-forward compensated FVF LDO regulator with no on-chip compensation capacitors. 89-97 - Sourav Naskar:
Complete design approach of a 3rd order continuous-time sigma-delta ADC with FIR feedback and low-noise low-distortion op-amp achieving 101.8 dB SNDR and -110dB THD. 98-106 - Fatma Nur Esirci, Alp Arslan Bayrakci:
Delay based hardware Trojan detection exploiting spatial correlations to suppress variations. 107-118 - Ruiming Xu, Zhongjie Guo, Ningmei Yu, Suiyang Liu:
A high-speed 13-bit two-step single-slope ADC for large array CMOS image sensors. 119-125 - Hui Xu, Jing Zhou, Ruijun Ma, Huaguo Liang, Zhengfeng Huang, Chaoming Liu:
LQNTL: Low-overhead quadruple-node-upset self-recovery latch based on triple-mode redundancy. 126-135 - Huijing Yang, Shichang Li, Mingyuan Ren:
A low offset low power CMOS dynamic comparator for analog to digital converters. 136-143 - Zehua Fang, Jinglin Han, Huaxinyu Wang:
Deep reinforcement learning assisted reticle floorplanning with rectilinear polygon modules for multiple-project wafer. 144-152 - Kaushik Das, Sambhu Nath Pradhan:
Hardware architecture design for complementary ensemble empirical mode decomposition algorithm. 153-164 - Malek Teib, Alexandre Malherbe, Edith Kussener:
Multi-harvesting smart solution for self-powered wearable objects: System-level model and transistor-level design. 165-172 - Bijan Alizadeh, Masoud Shiroei:
Automatic correction of RTL designs using a lightweight partial high level synthesis. 173-181
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-20 23:48 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
