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ORCIDJing Ye 0001
Person information
- affiliation: Chinese Academy of Sciences, Institute of Computing Technology, State Key Laboratory of Processors/State Key Laboratory of Computer Architecture, Beijing, China
Other persons with the same name
- Jing Ye — disambiguation page
- Jing Ye 0002
![[0000-0001-7256-9085]](https://dblp.org/img/orcid-mark.12x12.png "0000-0001-7256-9085")
— China University of Petroleum, College of Control Science and Engineering, Qingdao, China - Jing Ye 0003 — Zhejiang University School of Medicine, Children's Hospital, Department of Surgical ICU, Hangzhou, China
- Jing Ye 0004 — Chinese Academy of Sciences, Yunnan Observatories, Kunming, China (and 1 more)
- Jing Ye 0005 — Shenzhen MileBot Robotics Co., Ltd., Shenzhen, China (and 2 more)
- Jing Ye 0006 — Heriot-Watt University, School of Engineering and Physical Sciences, Edinburgh Joint Research Institute in Signal and Image Processing, Edinburgh, UK
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2020 – today
- 2025
[j22]Zhiteng Chao, Xindi Zhang, Junying Huang, Zizhen Liu, Yixuan Zhao, Jing Ye, Shaowei Cai, Huawei Li, Xiaowei Li:
A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow. Integr. 100: 102265 (2025)- [c55]Mingjun Wang, Hui Wang, Zizhen Liu, Feng Gu, Jianan Mu, Jiaping Tang, Jun Gao, Huawei Li, Jing Ye, Xiaowei Li:
ETPG: Efficient Transition Fault Simulation via Dual-Strategy Pattern Parallelism and Gate Restructuring. ASP-DAC 2025: 1321-1327 - 2024
- [j21]Zizhen Liu, Weiyang He, Chip-Hong Chang, Jing Ye, Huawei Li, Xiaowei Li:
SPFL: A Self-Purified Federated Learning Method Against Poisoning Attacks. IEEE Trans. Inf. Forensics Secur. 19: 6604-6619 (2024) - [c54]Zhiteng Chao, Xindi Zhang, Junying Huang, Jing Ye, Shaowei Cai, Huawei Li, Xiaowei Li:
A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT Solver. ASPDAC 2024: 503-508 - [c53]Jiaping Tang, Zizhen Liu, Jianan Mu, Feng Gu, Mingjun Wang, Wenxing Li, Jing Ye, Xiaowei Li, Huawei Li:
Accelerating Sequential Circuit Simulation with Spatial Locality Enhancement and Redundant Event Reduction. ATS 2024: 1-6 - [c52]Jianan Mu, Husheng Han, Shangyi Shi, Jing Ye, Zizhen Liu, Shengwen Liang, Meng Li, Mingzhe Zhang, Song Bian, Xing Hu, Huawei Li, Xiaowei Li:
Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption. DAC 2024: 26:1-26:6 - [c51]Han Yan, Shuai Chen, Junying Huang, Jing Ye, Huawei Li, Xiaowei Li:
A Fully Pipelined High-Performance Elliptic Curve Cryptography Processor for NIST P-256. ETS 2024: 1-4 - [c50]Feng Gu, Mingjun Wang, Jianan Mu, Zizhen Liu, Jiaping Tang, Hui Wang, Yonghao Wang, Jing Ye, Huawei Li, Xiaowei Li:
DDP-Fsim: Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelism. ICCAD 2024: 95:1-95:9 - [c49]Zhiteng Chao, Qinluan Dai, Jiale Li, Zizhen Liu, Wenxing Li, Hongqin Lyu, Jing Ye, Huawei Li, Xiaowei Li:
A Static Test Compaction Method Based on GCN Assisted Fault Gate Classification. ITC-Asia 2024: 1-6 - [c48]Mingjun Wang, Hui Wang, Jianan Mu, Zizhen Liu, Jun Gao, Jing Ye, Huawei Li, Xiaowei Li:
Efficient Functional Safety Method for Gate-Level Fine-Grained Digital Circuits with ISO-26262. ITC-Asia 2024: 1-6 - 2023
- [j20]Yipei Yang, Zongyue Wang, Jing Ye, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li, Yuan Cao:
Chosen ciphertext correlation power analysis on Kyber. Integr. 91: 10-22 (2023) - [j19]Jianan Mu, Yi Ren, Wen Wang, Yizhong Hu, Shuai Chen, Chip-Hong Chang, Junfeng Fan, Jing Ye, Yuan Cao, Huawei Li, Xiaowei Li:
Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(5): 1504-1517 (2023) - [j18]Yuan Cao, Wanyi Liu, Yue Zheng, Shuai Chen, Jing Ye, Lei Qian, Chip-Hong Chang:
A New Reconfigurable True Random Number Generator and Physical Unclonable Function Unified Chip With On-Chip Auto-Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4900-4913 (2023) - [j17]Zizhen Liu, Si Chen, Jing Ye, Junfeng Fan, Huawei Li, Xiaowei Li:
DHSA: efficient doubly homomorphic secure aggregation for cross-silo federated learning. J. Supercomput. 79(3): 2819-2849 (2023) - [c47]Zhiteng Chao, Senlin Wang, Pengyu Tian, Shuwen Yuan, Huawei Li, Jing Ye, Xiaowei Li:
A Distributed ATPG System Combining Test Compaction Based on Pure MaxSAT. ATS 2023: 1-6 - [c46]Huawei Li, Jing Ye, Wei Hu, Jiliang Zhang:
Message from the Chairs. ATS 2023: 1 - [c45]Jianan Mu, Huajie Tan, Shuai Chen, Min Cai, Jing Ye, Huawei Li, Xiaowei Li:
Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design. ATS 2023: 1-6 - [c44]Yipei Yang, Junying Huang, Zongyue Wang, Jing Ye, Zihao Sun, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li, Yuan Cao:
A Template Attack on Reduction Without Reference Device on Kyber. ATS 2023: 1-6 - [c43]Jianan Mu, Huajie Tan, Jiawen Wu, Haotian Lu, Chip-Hong Chang, Shuai Chen, Shengwen Liang, Jing Ye, Huawei Li, Xiaowei Li:
Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array. DATE 2023: 1-2 - [c42]Chaofang Ma, Jianan Mu, Jing Ye, Shuai Chen, Yuan Cao, Huawei Li, Xiaowei Li:
Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants. ETS 2023: 1-6 - [i3]Zizhen Liu, Weiyang He, Chip-Hong Chang, Jing Ye, Huawei Li, Xiaowei Li:
SPFL: A Self-purified Federated Learning Method Against Poisoning Attacks. CoRR abs/2309.10607 (2023) - 2022
- [j16]Yuan Cao, Wanyi Liu, Lan Qin, Bingqiang Liu, Shuai Chen, Jing Ye, Xianzhao Xia, Chao Wang:
Entropy Sources Based on Silicon Chips: True Random Number Generator and Physical Unclonable Function. Entropy 24(11): 1566 (2022) - [j15]Yuan Cao, Yanze Wu, Wen Wang, Xu Lu, Shuai Chen, Jing Ye, Chip-Hong Chang:
An Efficient Full Hardware Implementation of Extended Merkle Signature Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 69(2): 682-693 (2022) - [j14]Zhen Wang, Guofa Zhang, Peng Liu, Jing Ye, Jianhui Jiang:
Accurate Reliability Boundary Evaluation of Approximate Arithmetic Circuit. IEEE Trans. Very Large Scale Integr. Syst. 30(10): 1507-1518 (2022) - [c41]Jianan Mu, Yixuan Zhao, Zongyue Wang, Jing Ye, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li, Yuan Cao:
A Voltage Template Attack on the Modular Polynomial Subtraction in Kyber. ASP-DAC 2022: 672-677 - [c40]Yixiao Chen, Jinfeng Song, Shuai Chen, Yuan Cao, Jing Ye, Huawei Li, Xiaowei Li, Xin Lou, Enyi Yao:
Exploring the high-throughput and low-delay hardware design of SM4 on FPGA. ISOCC 2022: 211-212 - [c39]Zizhen Liu, Si Chen, Jing Ye, Junfeng Fan, Huawei Li, Xiaowei Li:
SASH: Efficient secure aggregation based on SHPRG for federated learning. UAI 2022: 1243-1252 - [i2]Zizhen Liu, Si Chen, Jing Ye, Junfeng Fan, Huawei Li, Xiaowei Li:
DHSA: Efficient Doubly Homomorphic Secure Aggregation for Cross-silo Federated Learning. CoRR abs/2208.07189 (2022) - 2021
- [j13]Xing Hu, Yang Zhao, Lei Deng, Ling Liang, Pengfei Zuo, Jing Ye, Yingyan Lin, Yuan Xie:
Practical Attacks on Deep Neural Networks by Memory Trojaning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(6): 1230-1243 (2021) - [c38]Ning Lin, Xiaoming Chen, Chunwei Xia, Jing Ye, Xiaowei Li:
ChaoPIM: A PIM-based Protection Framework for DNN Accelerators Using Chaotic Encryption. ATS 2021: 1-6 - [c37]Zhen Wang, Guofa Zhang, Jing Ye, Jianhui Jiang:
Reliability Evaluation of Approximate Arithmetic Circuits Based on Signal Probability. ITC-Asia 2021: 1-6 - [i1]Zizhen Liu, Si Chen, Jing Ye, Junfeng Fan, Huawei Li, Xiaowei Li:
Efficient Secure Aggregation Based on SHPRG For Federated Learning. CoRR abs/2111.12321 (2021) - 2020
- [j12]Qingli Guo, Jing Ye, Yu Hu, Guohe Zhang, Xiaowei Li, Huawei Li:
MultiPAD: A Multivariant Partition-Based Method for Audio Adversarial Examples Detection. IEEE Access 8: 63368-63380 (2020) - [j11]Qingli Guo, Jing Ye, Yiran Chen, Yu Hu, Yazhu Lan, Guohe Zhang, Xiaowei Li:
INOR - An Intelligent noise reduction method to defend against adversarial audio examples. Neurocomputing 401: 160-172 (2020) - [c36]Yipei Yang, Jing Ye, Yuan Cao, Jiliang Zhang, Xiaowei Li, Huawei Li, Yu Hu:
Survey: Hardware Trojan Detection for Netlist. ATS 2020: 1-6 - [c35]Jiliang Zhang, Shuang Peng, Yupeng Hu, Fei Peng, Wei Hu, Jinmei Lai, Jing Ye, Xiangqi Wang:
HRAE: Hardware-assisted Randomization against Adversarial Example Attacks. ATS 2020: 1-6 - [c34]Yixuan Zhao, Zhiteng Chao, Jing Ye, Wen Wang, Yuan Cao, Shuai Chen, Xiaowei Li, Huawei Li:
Optimization Space Exploration of Hardware Design for CRYSTALS-KYBER. ATS 2020: 1-6 - [c33]Jiliang Zhang, Chen Li, Jing Ye, Gang Qu:
Privacy Threats and Protection in Machine Learning. ACM Great Lakes Symposium on VLSI 2020: 531-536 - [c32]Qingli Guo, Jing Ye, Jiliang Zhang, Yu Hu, Xiaowei Li, Huawei Li:
Prediction Stability: A New Metric for Quantitatively Evaluating DNN Outputs. ACM Great Lakes Symposium on VLSI 2020: 537-542 - [c31]Zizhen Liu, Jing Ye, Xing Hu, Huawei Li, Xiaowei Li, Yu Hu:
Sequence Triggered Hardware Trojan in Neural Network Accelerator. VTS 2020: 1-6
2010 – 2019
- 2019
- [j10]Xiaowei Li, Wenjie Li, Jing Ye, Huawei Li, Yu Hu:
Scan Chain Based Attacks and Countermeasures: A Survey. IEEE Access 7: 85055-85065 (2019) - [j9]Qingli Guo, Jing Ye, Bing Li, Yu Hu, Xiaowei Li, Yazhu Lan, Guohe Zhang:
PUFPass: A password management mechanism based on software/hardware codesign. Integr. 64: 173-183 (2019) - [c30]Yang Zhao, Xing Hu, Shuangchen Li, Jing Ye, Lei Deng, Yu Ji, Jianyu Xu, Dong Wu, Yuan Xie:
Memory Trojan Attack on Neural Network Accelerators. DATE 2019: 1415-1420 - [c29]Kuozhong Zhang, Junying Huang, Jing Ye, Xiaochun Ye, Da Wang, Dongrui Fan, Huawei Li, Xiaowei Li, Zhimin Zhang:
iATPG: Instruction-level Automatic Test Program Generation for Vulnerabilities under DVFS attack. IOLTS 2019: 287-292 - [c28]Yipei Yang, Jing Ye, Xiaowei Li, Yinhe Han, Huawei Li, Yu Hu:
Implementation of Parametric Hardware Trojan in FPGA. ITC-Asia 2019: 37-42 - [c27]Junying Huang, Jing Ye, Xiaochun Ye, Da Wang, Dongrui Fan, Huawei Li, Xiaowei Li, Zhimin Zhang:
Instruction Vulnerability Test and Code Optimization Against DVFS Attack. ITC-Asia 2019: 49-54 - 2018
- [j8]Xiaowei Li, Guihai Yan, Jing Ye, Ying Wang:
Fault tolerance on-chip: a reliable computing paradigm using self-test, self-diagnosis, and self-repair (3S) approach. Sci. China Inf. Sci. 61(11): 112102:1-112102:17 (2018) - [j7]Yiming Zeng, Yu Hu, Shice Liu, Jing Ye, Yinhe Han, Xiaowei Li, Ninghui Sun:
RT3D: Real-Time 3-D Vehicle Detection in LiDAR Point Cloud for Autonomous Driving. IEEE Robotics Autom. Lett. 3(4): 3434-3440 (2018) - [j6]Jing Ye, Qingli Guo, Yu Hu, Xiaowei Li:
Deterministic and Probabilistic Diagnostic Challenge Generation for Arbiter Physical Unclonable Function. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(12): 3186-3197 (2018) - [c26]Wenjie Li, Jing Ye, Xiaowei Li, Huawei Li, Yu Hu:
Bias PUF based Secure Scan Chain Design. AsianHOST 2018: 31-36 - [c25]Jing Ye, Yu Hu, Xiaowei Li:
Hardware Trojan in FPGA CNN Accelerator. ATS 2018: 68-73 - [c24]Qingli Guo, Jing Ye, Yue Gong, Yu Hu, Xiaowei Li:
PUF Based Pay-Per-Device Scheme for IP Protection of CNN Model. ATS 2018: 115-120 - [c23]Beibei Jin, Yu Hu, Yiming Zeng, Qiankun Tang, Shice Liu, Jing Ye:
VarNet: Exploring Variations for Unsupervised Video Prediction. IROS 2018: 5801-5806 - [c22]Jing Ye, Yipei Yang, Yue Gong, Yu Hu, Xiaowei Li:
Grey Zone in Pre-Silicon Hardware Trojan Detection. ITC-Asia 2018: 79-84 - [c21]Jing Ye, Qingli Guo, Yu Hu, Huawei Li, Xiaowei Li:
Modeling attacks on strong physical unclonable functions strengthened by random number and weak PUF. VTS 2018: 1-6 - 2017
- [j5]Yu Hu, Jing Ye, Zhiping Shi, Xiaowei Li:
LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization. IEICE Trans. Inf. Syst. 100-D(2): 323-331 (2017) - [j4]Bing Li, Yu Hu, Ying Wang, Jing Ye, Xiaowei Li:
Power-Utility-Driven Write Management for MLC PCM. ACM J. Emerg. Technol. Comput. Syst. 13(3): 50:1-50:22 (2017) - [j3]Weina Lu, Yu Hu, Jing Ye, Xiaowei Li:
Going Cooler With Timing-Constrained TeSHoP: A Temperature Sensing-Based Hotspot-Driven Placement Technique for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 25(9): 2525-2537 (2017) - [c20]Jing Ye, Yue Gong, Yu Hu, Xiaowei Li:
Polymorphic PUF: Exploiting reconfigurability of CPU+FPGA SoC to resist modeling attack. AsianHOST 2017: 43-48 - [c19]Jing Ye, Qingli Quo, Yu Hu, Xiaowei Li:
Fault diagnosis of arbiter physical unclonable function. DATE 2017: 428-433 - [c18]Weina Lu, Wenyan Lu, Jing Ye, Yu Hu, Xiaowei Li:
Leveraging FVT-margins in design space exploration for FFGA-based CNN accelerators. FPL 2017: 1-4 - [c17]Jing Ye, Yu Hu, Xiaowei Li:
VPUF: Voter based physical unclonable function with high reliability and modeling attack resistance. IOLTS 2017: 74-79 - [c16]Jing Ye, Yue Gong, Yu Hu, Xiaowei Li:
Polymorphic PUF: Exploiting reconfigurability of CPU+FPGA SoC to resist modeling attack. IOLTS 2017: 205-206 - [c15]Yiming Zeng, Yu Hu, Shice Liu, Qiankun Tang, Jing Ye, Xiaowei Li:
GeoCueDepth: Exploiting geometric structure cues to estimate depth from a single image. IROS 2017: 17-22 - 2016
- [c14]Qingli Guo, Jing Ye, Yue Gong, Yu Hu, Xiaowei Li:
Efficient Attack on Non-linear Current Mirror PUF with Genetic Algorithm. ATS 2016: 49-54 - [c13]Jing Ye, Yu Hu, Xiaowei Li:
POSTER: Attack on Non-Linear Physical Unclonable Function. CCS 2016: 1751-1753 - [c12]Jing Ye, Yu Hu, Xiaowei Li:
DCPUF: Placement and Routing Constraint based Dynamically Configured Physical Unclonable Function on FPGA (Abstact Only). FPGA 2016: 279 - [c11]Weina Lu, Yu Hu, Jing Ye, Xiaowei Li:
TeSHoP: A Temperature Sensing based Hotspot-Driven Placement technique for FPGAs. FPL 2016: 1-4 - [c10]Jing Ye, Yu Hu, Xiaowei Li:
RPUF: Physical Unclonable Function with Randomized Challenge to resist modeling attack. AsianHOST 2016: 1-6 - 2015
- [j2]Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan:
Diagnosis and Layout Aware (DLA) Scan Chain Stitching. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 466-479 (2015) - [c9]Jing Ye, Yu Hu, Xiaowei Li:
OPUF: Obfuscation logic based physical unclonable function. IOLTS 2015: 156-161 - 2014
- [j1]Jing Ye, Yu Hu, Xiaowei Li, Wu-Tung Cheng, Yu Huang, Huaxing Tang:
Diagnose Failures Caused by Multiple Locations at a Time. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 824-837 (2014) - 2013
- [c8]Xiaolin Zhang, Jing Ye, Yu Hu, Xiaowei Li:
Capturing post-silicon variation by layout-aware path-delay testing. DATE 2013: 288-291 - [c7]Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan:
Diagnosis and Layout Aware (DLA) scan chain stitching. ITC 2013: 1-10 - 2011
- [c6]Jing Ye, Yu Hu, Xiaowei Li:
On diagnosis of multiple faults using compacted responses. DATE 2011: 679-684 - 2010
- [c5]Jing Ye, Xiaolin Zhang, Yu Hu, Xiaowei Li:
Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method. Asian Test Symposium 2010: 192-197 - [c4]Jing Ye, Yu Hu, Xiaowei Li:
Diagnosis of multiple arbitrary faults with mask and reinforcement effect. DATE 2010: 885-890
2000 – 2009
- 2008
- [c3]Fei Wang, Yu Hu, Yu Huang, Jing Ye, Xiaowei Li:
Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis. ATS 2008: 190-192 - [c2]Fei Wang, Yu Hu, Huawei Li, Xiaowei Li, Jing Ye, Yu Huang:
Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects. ITC 2008: 1-10 - [c1]Jing Ye, Fei Wang, Yu Hu, Xiaowei Li:
Diagnosis of Mask-Effect Multiple Timing Faults in Scan Chains. ITC 2008: 1
Coauthor Index
[j22] [c55] [j21] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [j20] [j19] [j17] [c47] [c45] [c44] [c43] [c42] [i3] [c41] [c40] [c39] [i2] [c38] [i1] [j12] [j11] [c36] [c34] [c32] [c31] [j10] [j9] [c29] [c28] [c27] [j8] [j7] [j6] [c26] [c25] [c24] [c22] [c21] [j5] [j4] [j3] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [j2] [c9] [j1] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
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