IEEE Transactions on Computers, Volume 49

Volume 49, Number 1, January 2000

Architecture

• 
  Johnson Kin, Munish Gupta, William H. Mangione-Smith:
  Filtering Memory References to Increase Energy Efficiency. 1-15

Application-Specific Integrated Circuits

• 
  Mitrajit Chatterjee, Savita Banerjee, Dhiraj K. Pradhan:
  Buffer Assignment Algorithms on Data Driven ASICs. 16-32

Computer Arithmetic

• 
  Asger Munk Nielsen, David W. Matula, Chung Nan Lyu, Guy Even:
  An IEEE Compliant Floating-Point Adder that Conforms with the Pipelined Packet-Forwarding Paradigm. 33-47

Testing

• 
  Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi:
  An Approach for Detecting Multiple Faulty FPGA Logic Blocks. 48-54

Fault Tolerance

• 
  Hagbae Kim, Kang G. Shin:
  Evaluation of Fault Tolerance Latency from Real-Time Application's Perspectives. 55-64

Loop Pipelining

• 
  Sissades Tongsima, Edwin Hsing-Mean Sha, Chantana Chantrapornchai, David R. Surma, Nelson L. Passos:
  Probabilistic Loop Scheduling for Applications with Uncertain Execution Time. 65-80

Brief Contributions

• 
  Tarek F. Abdelzaher, Kang G. Shin:
  Period-Based Load Partitioning and Assignment for Large Real-Time Applications. 81-87
• 
  Irith Pomeranz, Sudhakar M. Reddy:
  On Finding a Minimal Functional Description of a Finite-State Machine for Test Generation for Adjacent Machines. 88-94

Volume 49, Number 2, February 2000

• 
  Jean-Luc Gaudiot:
  Editor's Note. 97-99

Real-Time Systems

• 
  Stefan Poledna, Alan Burns, Andy J. Wellings, Peter Barrett:
  Replica Determinism and Flexible Scheduling in Hard Real-Time Dependable Systems. 100-111
• 
  Tei-Wei Kuo, Shao-Juen Ho:
  Similarity-Based Load Adjustment for Static Real-Time Transaction Systems. 112-126

Parallel I/O Systems

• 
  Lin-Wen Lee, Peter Scheuermann, Radek Vingralek:
  File Assignment in Parallel I/O Systems with Minimal Variance of Service Time. 127-140

Computer Arithmetic

• 
  Vassil S. Dimitrov, Graham A. Jullien, William C. Miller:
  Complexity and Fast Algorithms for Multiexponentiations. 141-147

Performance Analysis

• 
  Yi-Bing Lin, Wei-Ru Lai, Rong-Jaye Chen:
  Performance Analysis for Dual Band PCS Networks. 148-159

Brief Contributions

• 
  Alpesh Patel, Anthony J. Kusalik, Carl McCrosky:
  Area-Efficient VLSI Layouts for Binary Hypercubes. 160-169
• 
  Ahmad A. Hiasat:
  New Efficient Structure for a Modular Multiplier for RNS. 170-174
• 
  Irith Pomeranz, Sudhakar M. Reddy:
  On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits. 175-181
• 
  Khawar M. Zuberi, Kang G. Shin:
  Design and Implementation of Efficient Message Scheduling for Controller Area Network. 182-188

Volume 49, Number 3, March 2000

Computer Arithmetic

• 
  Sorin Cotofana, Stamatis Vassiliadis:
  Signed Digit Addition and Related Operations with Threshold Logic. 193-207
• 
  Zhen Luo, Margaret Martonosi:
  Accelerating Pipelined Integer and Floating-Point Accumulations in Configurable Hardware with Delayed Addition Techniques. 208-218

Multiple-Valued Logic

• 
  Noboru Takagi, Kyoichi Nakashima:
  Discrete Interval Truth Values Logic and Its Application. 219-229

Fault Diagnosis

• 
  Andrea Bondavalli, Silvano Chiaradonna, Felicita Di Giandomenico, Fabrizio Grandoni:
  Threshold-Based Mechanisms to Discriminate Transient from Intermittent Faults. 230-245

Interconnection Network

• 
  San-Yuan Wang, Yu-Chee Tseng:
  Algebraic Foundations and Broadcasting Algorithms for Wormhole-Routed All-Port Tori. 246-258

Brief Contributions

• 
  M. Cemil Azizoglu, Ömer Egecioglu:
  Lower Bounds on Communication Loads with Optimal Placements in Torus Networks. 259-266
• 
  Ugur Kalay, Douglas V. Hall, Marek A. Perkowski:
  A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits. 267-276
• 
  Ramesh C. Tekumalla, Premachandran R. Menon:
  On Redundant Path Delay Faults in Synchronous Sequential Circuits. 277-282
• 
  Scott D. Stoller:
  Leader Election in Asynchronous Distributed Systems. 283-284

Volume 49, Number 4, April 2000

Test Generation

• 
  Franco Fummi, Donatella Sciuto:
  A Hierarchical Test Generation Approach for Large Controllers. 289-302

Real-Time Scheduling

• 
  Marco Di Natale, John A. Stankovic:
  Scheduling Distributed Real-Time Tasks with Minimum Jitter. 303-316

Verification

• 
  T. Ramalingom, Krishnaiyan Thulasiraman, Anindya Das:
  A Matroid-Theoretic Solution to an Assignment Problem in the Conformance Testing of Communication Protocols. 317-330

Compiler Techniques

• 
  Jian Huang, David J. Lilja:
  Extending Value Reuse to Basic Blocks with Compiler Support. 331-347

FPGA Architecture

• 
  Michael Shyu, Guang-Ming Wu, Yu-Dong Chang, Yao-Wen Chang:
  Generic Universal Switch Blocks. 348-359

Logic Synthesis

• 
  Laura Heinrich-Litan, Paul Molitor:
  Least Upper Bounds for the Size of OBDDs Using Symmetry Properties. 360-368

Computer Architecture

• 
  Todd C. Mowry, Chi-Keung Luk:
  Understanding Why Correlation Profiling Improves the Predictability of Data Cache Misses in Nonnumeric Applications. 369-384

Volume 49, Number 5, May 2000

• 
  Jean-Luc Gaudiot:
  Editor's Note. 385-386

Computer Arithmetic

• 
  Michael J. Schulte, Earl E. Swartzlander Jr.:
  A Family of Variable-Precision Interval Arithmetic Processors. 387-397
• 
  Guy Even, Wolfgang J. Paul:
  On the Design of IEEE Compliant Floating Point Units. 398-413

Fault Tolerance

• 
  Christine Morin, Anne-Marie Kermarrec, Michel Banâtre, Alain Gefflaut:
  An Efficient and Scalable Approach for Implementing Fault-Tolerant DSM Architectures. 414-430

Fault-Tolerant Array Networks

• 
  Nobuo Tsuda:
  Fault-Tolerant Processor Arrays Using Additional Bypass Linking Allocated by Graph-Node Coloring. 431-442

Formal Verification

• 
  Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer:
  AQUILA: An Equivalence Checking System for Large Sequential Designs. 443-464

Reconfigurable Architectures

• 
  Hartej Singh, Ming-Hau Lee, Guangming Lu, Fadi J. Kurdahi, Nader Bagherzadeh, Eliseu M. Chaves Filho:
  MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications. 465-481

Databases

• 
  Anindya Datta, Sang Hyuk Son, Vijay Kumar:
  Is a Bird in the Hand Worth More than Two in the Bush? Limitations of Priority Cognizance in Conflict Resolution for Firm Real-Time Database Systems. 482-502

Brief Contributions

• 
  Alper Halbutogullari, Çetin Kaya Koç:
  Mastrovito Multiplier for General Irreducible Polynomials. 503-518
• 
  Francisco M. de Assis, Carlos Eduardo Pedreira:
  An Architecture for Computing Zech's Logarithms in GF(2^m). 519-525

Volume 49, Number 6, June 2000

Defect Tolerance of Digital Systems

• 
  Fabrizio Lombardi, Mariagiovanna Sami:
  Guest Editors' Introduction. 529-531
• 
  Israel Koren, Zahava Koren:
  Incorporating Yield Enhancement into the Floorplanning Process. 532-541
• 
  Tadayoshi Horita, Itsuo Takanami:
  Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions. 542-552
• 
  Chor Ping Low:
  An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI Arrays. 553-559
• 
  Cecilia Metra, Michele Favalli, Bruno Riccò:
  Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines. 560-574
• 
  Claude Thibeault:
  On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults. 575-587
• 
  W. Lynn Gallagher, Earl E. Swartzlander Jr.:
  Fault-Tolerant Newton-Raphson and Goldschmidt Dividers Using Time Shared TMR. 588-595

Regular Papers

• 
  Irith Pomeranz, Sudhakar M. Reddy:
  Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits. 596-607
• 
  B. John Oommen, T. Dale Roberts:
  Continuous Learning Automata Solutions to the Capacity Assignment Problem. 608-620

Volume 49, Number 7, July 2000

Computer Arithmetic

• 
  Israel Koren, Peter Kornerup:
  Guest Editors' Introduction - Special Issue on Computer Arithmetic. 625-627
• 
  Milos D. Ercegovac, Tomás Lang, Jean-Michel Muller, Arnaud Tisserand:
  Reciprocation, Square Root, Inverse Square Root, and Some Elementary Functions Using Small Multipliers. 628-637
• 
  Guy Even, Peter-Michael Seidel:
  A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication. 638-650
• 
  Michael Parks:
  Number-Theoretic Test Generation for Directed Rounding. 651-658
• 
  Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald:
  Self-Timed Carry-Lookahead Adders. 659-672
• 
  Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos:
  High-Speed Parallel-Prefix Modulo 2n-1 Adders. 673-680
• 
  Michael J. Schulte, Pablo I. Balzola, Ahmet Akkas, Robert W. Brocato:
  Integer Multiplication with Overflow Detection or Saturation. 681-691
• 
  Wen-Chang Yeh, Chein-Wei Jen:
  High-Speed Booth Encoded Parallel Multiplier Design. 692-701
• 
  John N. Coleman, E. I. Chester, Christopher I. Softley, Jiri Kadlec:
  Arithmetic on the European Logarithmic Microprocessor. 702-715
• 
  Chichyang Chen, Rui-Lin Chen, Chih-Huan Yang:
  Pipelined Computation of Very Large Word-Length LNS Addition/Subtraction with Polynomial Hardware Cost. 716-726
• 
  Elisardo Antelo, Tomás Lang, Javier D. Bruguera:
  Very-High Radix Circular CORDIC: Vectoring and Unified Rotation/Vectoring. 727-739
• 
  Marc Joye, Sung-Ming Yen:
  Optimal Left-to-Right Binary Signed-Digit Recoding. 740-748
• 
  M. Anwarul Hasan:
  Look-Up Table-Based Large Finite Field Multiplication in Memory Constrained Cryptosystems. 749-758

Brief Contributions

• 
  Milos D. Ercegovac, Laurent Imbert, David W. Matula, Jean-Michel Muller, Guoheng Wei:
  Improving Goldschmidt Division, Square Root, and Square Root Reciprocal. 759-763
• 
  Erkay Savas, Çetin Kaya Koç:
  The Montgomery Modular Inverse-Revisited. 763-766

Volume 49, Number 8, August 2000

• 
  Saied Hosseini-Khayat:
  On Optimal Replacement of Nonuniform Cache Objects. 769-778
• 
  Ravi R. Iyer, Laxmi N. Bhuyan:
  Design and Evaluation of a Switch Cache Architecture for CC-NUMA Multiprocessors. 779-797
• 
  Guang R. Gao, Vivek Sarkar:
  Location Consistency-A New Memory Model and Cache Consistency Protocol. 798-813
• 
  Thomas M. Conte, Sumedh W. Sathaye:
  Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility. 814-825
• 
  Paola Bertolazzi, Giuseppe Di Battista, Walter Didimo:
  Computing Orthogonal Drawings with the Minimum Number of Bends. 826-840
• 
  Brian Field, Taieb Znati, Daniel Mossé:
  VV-NET: A Versatile Network Architecture for Flexible Delay Guarantees in Real-Time Networks. 841-858

Brief Contributions

• 
  Christiane Frougny:
  On-the-Fly Algorithms and Sequential Machines. 859-863

Volume 49, Number 9, September 2000

• 
  Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
  Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis. 865-885
• 
  Cristian Constantinescu:
  Teraflops Supercomputer: Architecture and Validation of the Fault Tolerance Mechanisms. 886-894
• 
  Hideo Fujiwara:
  A New Class of Sequential Circuits with Combinational Test Generation Complexity. 895-905
• 
  Frank Liberato, Rami G. Melhem, Daniel Mossé:
  Tolerance to Multiple Transient Faults for Aperiodic Tasks in Hard Real-Time Systems. 906-914
• 
  Xing Du, Xiaodong Zhang, Zhichun Zhu:
  Memory Hierarchy Considerations for Cost-Effective Cluster Computing. 915-933
• 
  Chia-Lin Yang, Barton Sano, Alvin R. Lebeck:
  Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions. 934-946
• 
  Ching-Chih Han, Kang G. Shin, Sang Kyun Yun:
  On Load Balancing in Multicomputer/Distributed Systems Equipped with Circuit or Cut-Through Switching Capability. 947-957

Brief Contributions

• 
  Meng-Lai Yin, Douglas M. Blough, Lubomir Bic:
  A Dependability Analysis for Systems with Global Spares. 958-963
• 
  Sulaiman Al-Bassam:
  Another Method for Constructing t-EC/AUED Codes. 964-966
• 
  Sung-Ming Yen, Marc Joye:
  Checking Before Output May Not Be Enough Against Fault-Based Cryptanalysis. 967-970
• 
  Pao-Yuan Chang, Deng-Jyi Chen, Krishna M. Kavi:
  Multimedia File Allocation on VC Networks Using Multipath Routing. 971-977
• 
  Chiuyuan Chen, Frank K. Hwang:
  The Minimum Distance Diagram of Double-Loop Networks. 977-979
• 
  Hsien-Sheng Hsiao, Yeh-Hao Chin, Wei-Pang Yang:
  Reaching Fault Diagnosis Agreement under a Hybrid Fault Model. 980-986
• 
  Saravut Charcranoon, Thomas G. Robertazzi, Serge Luryi:
  Parallel Processor Configuration Design with Processing/Transmission Costs. 987-991
• 
  Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya:
  Isomorph-Redundancy in Sequential Circuits. 992-997
• 
  Chenggong Charles Fan, Jehoshua Bruck:
  Tolerating Multiple Faults in Multistage Interconnection Networks with Minimal Extra Stages. 998-1004
• 
  Li Sheng, Jie Wu:
  A Note on 'A Tight Lower Bound on the Number of Channels Required for Deadlock-Free Wormhole Routing'. 1005

Volume 49, Number 10, October 2000

• 
  Jean-Luc Gaudiot:
  Editor's Note. 1009-1012
• 
  Evangelos Kranakis, Andrzej Pelc:
  Better Adaptive Diagnosis of Hypercubes. 1013-1020
• 
  Keqin Li, Yi Pan:
  Probabilistic Analysis of Scheduling Precedence Constrained Parallel Tasks on Multicomputers with Contiguous Processor Allocation. 1021-1030
• 
  Mohammad H. Azadmanesh, Roger M. Kieckhafer:
  Exploiting Omissive Faults in Synchronous Approximate Agreement. 1031-1042
• 
  Bernhard Balkenhol, Stefan Kurtz:
  Universal Data Compression Based on the Burrows-Wheeler Transformation: Theory and Practice. 1043-1053
• 
  Jun Zhao, V. Swamy Irrinki, Mukesh Puri, Fabrizio Lombardi:
  Testing SRAM-Based Content Addressable Memories. 1054-1063
• 
  M. Anwarul Hasan, Amr G. Wassal:
  VLSI Algorithms, Architectures, and Implementation of a Versatile GF(2^m) Processor. 1064-1073
• 
  Naofumi Takagi, Seiji Kuwahara:
  A VLSI Algorithm for Computing the Euclidean Norm of a 3D Vector. 1074-1082
• 
  Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian:
  Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays. 1083-1099
• 
  Jovan Dj. Golic, Andrew J. Clark, Ed Dawson:
  Generalized Inversion Attack on Nonlinear Filter Generators. 1100-1109

Brief Contributions

• 
  Ching-Chih Han, Chao-Ju Hou, Kar Shun Tsoi, Sean Ho:
  Dynamic Establishment and Termination of Real-Time Message Streams in Dual-Bus Networks. 1110-1119
• 
  Chin-Liang Wang, Jyh-Huei Guo:
  New Systolic Arrays for C + AB2, Inversion, and Division in GF(2^m). 1120-1125
• 
  Akhil Kumar:
  An Efficient SuperGrid Protocol for High Availability and Load Balancing. 1126-1133
• 
  Sangho Oh, Chang Han Kim, Jongin Lim, Dong Hyeon Cheon:
  Efficient Normal Basis Multipliers in Composite Fields. 1133-1138
• 
  Kun-Jin Lin, Cheng-Wen Wu:
  A Low-Power CAM Design for LZ Data Compression. 1139-1145
• 
  Marco Tomassini, Moshe Sipper, Mathieu Perrenoud:
  On the Generation of High-Quality Random Numbers by Two-Dimensional Cellular Automata. 1146-1151
• 
  John N. Coleman, E. I. Chester, Christopher I. Softley, Jiri Kadlec:
  Corrections to 'Arithmetic on the European Logarithmic Microprocessor'. 1152

Volume 49, Number 11, November 2000

1997 IEEE Real-Time Technologies and Applications Symposium

• 
  Ragunathan Rajkumar:
  Guest Editor's Introduction: 1997 IEEE Real-Time Technologies and Applications Symposium. 1153-1154
• 
  Dong-In Kang, Richard Gerber, Manas Saksena:
  Parametric Design Synthesis of Distributed Embedded Systems. 1155-1169
• 
  Tarek F. Abdelzaher, Ella M. Atkins, Kang G. Shin:
  QoS Negotiation in Real-Time Systems and Its Application to Automated Flight Control. 1170-1183
• 
  Monica Brockmeyer, Farnam Jahanian, Constance L. Heitmeyer, Elly Winner:
  A Flexible, Extensible Simulation Environment for Testing Real-Time Specifications. 1184-1201
• 
  Chia Shen, Ichiro Mizunuma:
  RT-CRM: Real-Time Channel-Based Reflective Memory. 1202-1214
• 
  Sung-Whan Moon, Jennifer Rexford, Kang G. Shin:
  Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches. 1215-1227

Papers

• 
  Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer:
  Novel Test Pattern Generators for Pseudoexhaustive Testing. 1228-1240
• 
  Tei-Wei Kuo, Aloysius K. Mok:
  Real-Time Data Semantics and Similarity-Based Concurrency Control. 1241-1254
• 
  Sally A. McKee, William A. Wulf, James H. Aylor, Robert H. Klenke, Maximo H. Salinas, Sung I. Hong, Dee A. B. Weikle:
  Dynamic Access Ordering for Streamed Computations. 1255-1271
• 
  Ramesh Karri, Kyosun Kim, Miodrag Potkonjak:
  Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors. 1272-1284

Brief Contributions

• 
  Elena Dubrova, Jon C. Muzio:
  Easily Testable Multiple-Valued Logic Circuits Derived from Reed-Muller Circuits. 1285-1289

Comments

• 
  Elena Dubrova, Luca Macchiarulo:
  A Comment on 'Graph-Based Algorithm for Boolean Function Manipulation'. 1290-1292

Volume 49, Number 12, December 2000

• 
  Hyesook Lim, Vincenzo Piuri, Earl E. Swartzlander Jr.:
  A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms. 1297-1309
• 
  Stephan Olariu, Maria Cristina Pinotti, Si-Qing Zheng:
  An Optimal Hardware-Algorithm for Sorting Using a Fixed-Size Parallel Sorting Device. 1310-1324
• 
  Umesh Krishnaswamy, Isaac D. Scherson:
  A Framework for Computer Performance Evaluation Using Benchmark Sets. 1325-1338
• 
  Tsan-sheng Hsu, Joseph C. Lee, Dian Rae Lopez, William A. Royce:
  Task Allocation on a Network of Processors. 1339-1353
• 
  William E. Cohen, David W. Hyde, Rhonda Kay Gaede:
  An Optical Bus-Based Distributed Dynamic Barrier Mechanism. 1354-1365

Brief Contributions

• 
  Satoshi Fujita:
  Neighborhood Information Dissemination in the Star Graph. 1366-1370
• 
  Yu-Liang Wu, Hongbing Fan, Malgorzata Marek-Sadowska, C. K. Wong:
  OBDD Minimization Based on Two-Level Representation of Boolean Functions. 1371-1379