Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDACM Transactions on Reconfigurable Technology and Systems, Volume 17
Volume 17, Number 1, March 2024
- Anupreetham Anupreetham
, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-Sun Seo:
High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design. 1:1-1:20 - Zimeng Fan, Wei Hu, Fang Liu, Dian Xu, Hong Guo, Yanxiang He, Min Peng:
A Hardware Design Framework for Computer Vision Models Based on Reconfigurable Devices. 2:1-2:31
- Fabio Maschi, Gustavo Alonso:
Strega: An HTTP Server for FPGAs. 3:1-3:27 - Yunhui Qiu, Yiqing Mao, Xuchen Gao, Sichao Chen, Jiangnan Li, Wenbo Yin, Lingli Wang:
FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism. 4:1-4:26 - John A. Kalomiros, John V. Vourvoulakis, Stavros Vologiannidis:
A Hardware Accelerator for the Semi-Global Matching Stereo Algorithm: An Efficient Implementation for the Stratix V and Zynq UltraScale+ FPGA Technology. 5:1-5:25 - Miguel Reis, Mário P. Véstias, Horácio C. Neto:
Designing Deep Learning Models on FPGA with Multiple Heterogeneous Engines. 6:1-6:30 - Rafael Fão de Moura, Luigi Carro:
Reprogrammable Non-Linear Circuits Using ReRAM for NN Accelerators. 7:1-7:19 - Alexandre Honorat, Mickaël Dardaillon, Hugo Miomandre, Jean-François Nezan:
Automated Buffer Sizing of Dataflow Applications in a High-level Synthesis Workflow. 8:1-8:26 - Louis Noyez, Nadia El Mrabet, Olivier Potin, Pascal Véron:
Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E2. 9:1-9:31 - Parastoo Soleimani, David W. Capson, Kin Fun Li:
A Partitioned CAM Architecture with FPGA Acceleration for Binary Descriptor Matching. 10:1-10:21 - Olivia Weng, Gabriel Marcano, Vladimir Loncar, Alireza Khodamoradi, G. Abarajithan, Nojan Sheybani, Andres Meza, Farinaz Koushanfar, Kristof Denolf, Javier Mauricio Duarte, Ryan Kastner:
Tailor: Altering Skip Connections for Resource-Efficient Inference. 11:1-11:23 - Jennifer Hasler, Cong Hao:
Programmable Analog System Benchmarks Leading to Efficient Analog Computation Synthesis. 12:1-12:25
- Diana Göhringer, Georgios Keramidas, Akash Kumar:
Introduction to the FPL 2021 Special Section. 13:1-13:2 - Stefan Nikolic, Paolo Ienne:
Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns. 14:1-14:39 - Zhengyan Liu, Qiang Liu, Shun Yan, Ray C. C. Cheung:
An Efficient FPGA-based Depthwise Separable Convolutional Neural Network Accelerator with Hardware Pruning. 15:1-15:20 - Jeffrey Chen, Sang-Woo Jun, Sehwan Hong, Warrick He, Jinyeong Moon:
Eciton: Very Low-power Recurrent Neural Network Accelerator for Real-time Inference at the Edge. 16:1-16:25
- Sajjad Rostami Sani, Andy Gean Ye:
Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm. 17:1-17:29 - Yonggen Li, Xin Li, Haibin Shen, Jicong Fan, Yanfeng Xu, Kejie Huang:
An All-digital Compute-in-memory FPGA Architecture for Deep Learning Acceleration. 18:1-18:27
Volume 17, Number 2, June 2024
- Andreas Koch, Kentaro Sano:
Introduction to the Special Issue on FPL 2022. 19:1-19:3 - Xijie Jia, Yu Zhang, Guangdong Liu, Xinlin Yang, Tianyu Zhang, Jia Zheng, Dongdong Xu, Zhuohuan Liu, Mengke Liu, Xiaoyang Yan, Hong Wang, Rongzhang Zheng, Li Wang, Dong Li, Satyaprakash Pareek, Jian Weng, Lu Tian, Dongliang Xie, Hong Luo, Yi Shan:
XVDPU: A High-Performance CNN Accelerator on the Versal Platform Powered by the AI Engine. 20:1-20:24 - Yuanlong Xiao, Dongjoon Park, Zeyu Jason Niu, Aditya Hota, André DeHon:
ExHiPR: Extended High-Level Partial Reconfiguration for Fast Incremental FPGA Compilation. 21:1-21:28 - Jonas Dann, Daniel Ritter, Holger Fröning:
GraphScale: Scalable Processing on FPGAs for HBM and Large Graphs. 22:1-22:23 - Babar Khan, Carsten Heinz, Andreas Koch:
The Open-source DeLiBA2 Hardware/Software Framework for Distributed Storage Accelerators. 23:1-23:32 - Jens Trautmann, Paul Krüger, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Design, Calibration, and Evaluation of Real-time Waveform Matching on an FPGA-based Digitizer at 10 GS/s. 24:1-24:28
- Geng Yang, Jie Lei, Zhenman Fang, Yunsong Li, Jiaqing Zhang, Weiying Xie:
HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural Networks. 25:1-25:24 - Nils Albartus, Maik Ender, Jan-Niklas Möller, Marc Fyrbiak, Christof Paar, Russell Tessier:
On the Malicious Potential of Xilinx's Internal Configuration Access Port (ICAP). 26:1-26:28 - Theodoros Trochatos, Anthony Etim, Jakub Szefer:
Covert-channels in FPGA-enabled SmartSSDs. 27:1-27:23 - Emanuele Del Sozzo, Davide Conficconi, Kentaro Sano:
Across Time and Space: Senju's Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs. 28:1-28:33 - Tianyou Bao, Pengzhou He, Jiafeng Xie, H. S. Jacinto:
AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-Based Lightweight PQC. 29:1-29:23
- Konstantin Hoßfeld, Hans Jakob Damsgaard, Jari Nurmi, Michaela Blott, Thomas B. Preußer:
High-efficiency Compressor Trees for Latest AMD FPGAs. 30:1-30:32 - Siva Satyendra Sahoo, Salim Ullah, Akash Kumar:
AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming. 31:1-31:28 - Kexin Li, Shaoxian Xu, Zhiyuan Shao, Ran Zheng, Xiaofei Liao, Hai Jin:
ScalaBFS2: A High-performance BFS Accelerator on an HBM-enhanced FPGA Chip. 32:1-32:39 - Chris Keilbart, Yuhui Gao, Martin Chua, Eric Matthews, Steven J. E. Wilton, Lesley Shannon:
Designing an IEEE-Compliant FPU that Supports Configurable Precision for Soft Processors. 33:1-33:32 - Barry de Bruin, Kanishkan Vadivel, Mark Wijtvliet, Pekka Jääskeläinen, Henk Corporaal:
R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA. 34:1-34:34 - Sichao Chen, Chang Cai, Su Zheng, Jiangnan Li, Guowei Zhu, Jingyuan Li, Yazhou Yan, Yuan Dai, Wenbo Yin, Lingli Wang:
HierCGRA: A Novel Framework for Large-scale CGRA with Hierarchical Modeling and Automated Design Space Exploration. 35:1-35:31
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-07-29 21:18 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
