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ORCIDKenneth Y. Yun
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- affiliation: University of California, San Diego, USA
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2010 – 2019
- 2010
[c32]Jaewook Shim, Kenneth Y. Yun, Rene L. Cruz:
An efficient wireless switching architecture. WTS 2010: 1-9
2000 – 2009
- 2008
- [c31]Manish Amde, Jaewook Shim, Joel Marciano, Kenneth Y. Yun, Rene L. Cruz:
A low SINR synchronization system for direct-sequence spread-spectrum communications: radio prototype, verification testbed and experimental results. TRIDENTCOM 2008: 25 - 2007
- [c30]Jaewook Shim, Manish Amde, Kenneth Y. Yun, Rene L. Cruz:
Synchronization at Low SINR in Asynchronous Direct-Sequence Spread-Spectrum Communications. ICSNC 2007: 26 - 2006
- [c29]Manish Amde, Joel Marciano, Sushil K. Singh, Cahit Akin, Rene L. Cruz, Kenneth Y. Yun:
Packet detection and acquisition at low SINR in spread-spectrum based wireless communications. WCNC 2006: 1765-1770 - 2004
- [c28]Sushil K. Singh, Viet L. Do, Kevin W. James, Kenneth Y. Yun, Rene L. Cruz, Manish Amde:
QoS Enabled Broadband Access Through Optical Rings. LCN 2004: 421-422 - 2001
- [j12]Kenneth S. Stevens, Shai Rotem, Ran Ginosar, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun, Rakefet Kol, Charles Dike, Marly Roncken:
An asynchronous instruction length decoder. IEEE J. Solid State Circuits 36(2): 217-228 (2001) - [j11]Kenneth Y. Yun:
A Terabit Multiservice Switch. IEEE Micro 21(1): 58-70 (2001) - 2000
- [j10]Kenneth Y. Yun, Kevin W. James, Robert H. Fairlie-Cuninghame, Supratik Chakraborty
, Rene L. Cruz:
A self-timed real-time sorting network. IEEE Trans. Very Large Scale Integr. Syst. 8(3): 356-363 (2000)
1990 – 1999
- 1999
- [j9]Supratik Chakraborty, David I. Dill, Kenneth Y. Yun:
Min-max timing analysis and an application to asynchronous circuits. Proc. IEEE 87(2): 332-346 (1999) - [j8]Kenneth Y. Yun, David L. Dill:
Automatic synthesis of extended burst-mode circuits. I.(Specification and hazard-free implementations). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(2): 101-117 (1999) - [j7]Kenneth Y. Yun, David L. Dill:
Automatic synthesis of extended burst-mode circuits. II. (Automaticsynthesis). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(2): 118-132 (1999) - [j6]Supratik Chakraborty, Kenneth Y. Yun, David L. Dill:
Timing analysis of asynchronous systems using time separation of events. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(8): 1061-1076 (1999) - [j5]Wei-Chun Chou, Peter A. Beerel, Kenneth Y. Yun:
Average-case technology mapping of asynchronous burst-mode circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(10): 1418-1434 (1999) - [j4]Kenneth Y. Yun, Ayoob E. Dooply:
Pausible clocking-based heterogeneous systems. IEEE Trans. Very Large Scale Integr. Syst. 7(4): 482-488 (1999) - [c27]Ayoob E. Dooply, Kenneth Y. Yun:
Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines. ARVLSI 1999: 200-214 - [c26]Kenneth Y. Yun, Ayoob E. Dooply:
Optimal Evaluation Clocking of Self-Resetting Domino Pipelines. ASP-DAC 1999: 121-124 - [c25]Kenneth Y. Yun:
Recent Advances in Asynchronous Design Methodologies. ASP-DAC 1999: 253- - [c24]Shai Rotem, Ken S. Stevens, Charles Dike, Marly Roncken, Boris Agapiev, Ran Ginosar, Rakefet Kol, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun:
RAPPID: An Asynchronous Instruction Length Decoder. ASYNC 1999: 60-70 - [c23]Erik Brunvand, Steven M. Nowick, Kenneth Y. Yun:
Practical Advances in Asynchronous Design and in Asynchronous/Synchronous Interfaces. DAC 1999: 104-109 - [c22]Kevin W. James, Kenneth Y. Yun:
A 40 Gb/s packet switching architecture with fine-grained priorities. ICCCN 1999: 148-153 - [c21]Viet L. Do, Kenneth Y. Yun:
A scalable priority queue manager architecture for output-buffered ATM switches. ICCCN 1999: 154-160 - 1998
- [j3]Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas Devadas:
BDD-based synthesis of extended burst-mode controllers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(9): 782-792 (1998) - [j2]Viet L. Do, Kenneth Y. Yun:
A low-power VLSI architecture for full-search block-matching motion estimation. IEEE Trans. Circuits Syst. Video Technol. 8(4): 393-398 (1998) - [j1]Kenneth Y. Yun, Peter A. Beerel, Vida Vakilotojar, Ayoob E. Dooply, Julio Arceo:
The design and verification of a high-performance low-control-overhead asynchronous differential equation solver. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 643-655 (1998) - [c20]Kevin W. James, Kenneth Y. Yun:
Average-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. ASYNC 1998: 70-79 - [c19]Wei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Ken S. Stevens, Kenneth Y. Yun:
Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. ASYNC 1998: 80- - [c18]Supratik Chakraborty, Kenneth Y. Yun, David L. Dill:
Practical timing analysis of asynchronous circuits using time separation of events. CICC 1998: 455-458 - [c17]Kenneth Y. Yun, Supratik Chakraborty, Kevin W. James, Robert H. Fairlie-Cuninghame, Rene L. Cruz:
A self-timed real-time sorting network. ICCD 1998: 427-434 - 1997
- [c16]Supratik Chakraborty, David L. Dill, Kun-Yung Chang, Kenneth Y. Yun:
Timing Analysis of Extended Burst-Mode Circuits. ASYNC 1997: 101-111 - [c15]Kenneth Y. Yun, Ayoob E. Dooply, Julio Arceo, Peter A. Beerel, Vida Vakilotojar:
The Design and Verification of A High-Performance Low-Control-Overhead Asynchronous Differential Equation Solver. ASYNC 1997: 140- - [c14]Steven M. Nowick, Kenneth Y. Yun, Ayoob E. Dooply, Peter A. Beerel:
Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders. ASYNC 1997: 210- - [c13]Erik Brunvand, Steven M. Nowick, Kenneth Y. Yun:
Practical Advances in Asynchronous Design. ICCD 1997: 662-668 - 1996
- [c12]Kenneth Y. Yun, Peter A. Beerel, Julio Arceo:
High-performance asynchronous pipeline circuits. ASYNC 1996: 17-28 - [c11]Peter A. Beerel, Kenneth Y. Yun, Wei-Chun Chou:
Optimizing average-case delay in technology mapping of burst-mode circuits. ASYNC 1996: 244-260 - [c10]Peter A. Beerel, Wei-Chun Chou, Kenneth Y. Yun:
A heuristic covering technique for optimizing average-case delay in the technology mapping of asynchronous burst-mode circuits. EURO-DAC 1996: 284-289 - [c9]Kenneth Y. Yun:
Automatic synthesis of extended burst-mode circuits using generalized C-elements. EURO-DAC 1996: 290-295 - [c8]Kenneth Y. Yun, Ryan P. Donohue:
Pausible Clocking: A First Step Toward Heterogeneous Systems. ICCD 1996: 118-123 - 1995
- [c7]Peter A. Beerel, Kenneth Y. Yun, Steven M. Nowick, Pei-Chuan Yeh:
Estimation and bounding of energy consumption in burst-mode control circuits. ICCAD 1995: 26-33 - [c6]Kenneth Y. Yun, David L. Dill:
A high-performance asynchronous SCSI controller. ICCD 1995: 44-49 - 1994
- [c5]Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas Devadas:
Performance-driven synthesis of asynchronous controllers. ICCAD 1994: 550-557 - 1993
- [c4]Kenneth Y. Yun, David L. Dill:
Unifying synchronous/asynchronous state machine synthesis. ICCAD 1993: 255-260 - 1992
- [c3]Kenneth Y. Yun, David L. Dill:
Automatic synthesis of 3D asynchronous state machines. ICCAD 1992: 576-580 - [c2]Steven M. Nowick, Kenneth Y. Yun, David L. Dill:
Practical Asynchronous Controller Design. ICCD 1992: 341-345 - [c1]Kenneth Y. Yun, David L. Dill, Steven M. Nowick:
Synthesis of 3D Asynchronous State Machines. ICCD 1992: 346-350
Coauthor Index
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