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ORCIDICCD 1992: Cambridge, MA, USA
- Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '92, Cambridge, MA, USA, October 11-14, 1992. IEEE Computer Society 1992, ISBN 0-8186-3110-4
Keynote Address
- Abbas El Gamal:
Field-Programmable Integrted Circuits - Overview and Future Trends. 2
Architecture Plenary
- Derrick Meyer:
Alpha Architecture: Hardware Implementation and Software Programming Implications. 4-5
CAD Plenary
- Aart J. de Geus:
High Level Design: A Design Vision for the 90's. 8
Design and Test Plenary
- Gordon D. Robinson:
Design and Test - The Next Problems. 10
Computer-Based Systems Plenary
- Stephanie White, Mack W. Alford, Brian McCay, David Oliver, Colin Tully, Julian Holtzman, C. Stephen Kuehl, David Owens, Allan Willey:
Trends in Computer-Based Systems Engineering. 12-15
Tutorial on Embedded Systems
- Wayne H. Wolf, Ernest Frey:
Tutorial on Embedded System Design. 18-21
Synthesis for Testability
- Daniel Brand, Vijay S. Iyengar:
Identification of Single Gate Delay Fault Redundancies. 24-28 - Tien-Chien Lee, Wayne H. Wolf, Niraj K. Jha, John M. Acken:
Behavioral Synthesis for Easy Testability in Data Path Allocation. 29-32 - Marek A. Perkowski, Laszlo Csanky, Andisheh Sarabi, Ingo Schäfer:
Fast Minimization of Mixed-Polarity AND/XOR Canonical Networks. 33-36
Timing Analysis and Optimization
- Srinivas Devadas, Horng-Fei Jyu, Kurt Keutzer, Sharad Malik
:
Statistical Timing Analysis of Combinational Circuits. 38-43 - Lukas P. P. P. van Ginneken:
Fanin Ordering in Multi-Slot Timing Analysis. 44-47 - Kenneth L. McMillan, David L. Dill:
Algorithms for Interface Timing Verification. 48-51
Design and Test of Multichip Modules
- Jeffery Banker:
Designing ASICs for Use with Multichip Modules. 54-58 - Yervant Zorian:
A Universal Testability Strategy for Multi-Chip Modules Based on BIST and Boundary-Scan. 59-66
VLSI Design
- Gopal Lakhani:
VLSI Design of Modulo Adders/Subtractors. 68-71 - Thou-Ho Chen, Liang-Gee Chen, Yi-Shing Chang:
Design of Concurrent Error-Detectable VLSI-Based Array Dividers. 72-75 - Erik Brunvand, Nick Michell, Kent F. Smith:
A Comparison of Self-Timed Design Using FPGA, CMOS, and GaAs Technologies. 76-80 - Charles A. Zukowski, Ying-Wen Bai:
Implementing a High-Frequency Pattern Generator Based on Combinational Merging. 81-84
Routing and Mapping in FPGAs
- Martine D. F. Schlag, Jackson Kong, Pak K. Chan:
Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs. 86-90 - Steven Trimberger, Mon-Ren Chene:
Placement-Based Partitioning for Lookup-Table-Based FPGAs. 91-94 - Narasimha B. Bhat, Dwight D. Hill:
Routable Technologie Mapping for LUT FPGAs. 95-98 - Benjamin Tseng, Jonathan Rose, Stephen Brown:
Improving FPGA Routing Architectures Using Architecture and CAD Interactions. 99-104
Computer Arithmetic
- Vijay K. Jain, Gibert E. Perez, Earl E. Swartzlander Jr.:
Arithmetic Error Analysis of a new Reciprocal Cell. 106-109 - Jien-Chung Lo:
Reliable Floating-Point Arithmetic Algorithms for Berger Encoded Operands. 110-113 - Jalil Fadavi-Ardekani:
MxN Booth Encoded Multiplier Generator Using Optimized Wallace Trees. 114-117 - Philip E. Madrid, Brian Millar, Earl E. Swartzlander Jr.:
Modified Booth Algorithm for High Radix Multiplication. 118-121
Computer-Based Systems
- Mani B. Srivastava, Trevor I. Blumenau, Robert W. Brodersen:
Design and Implementation of a Robot Control System Using a Unified Hardware-Software Rapid Prototyping Framework. 124-127 - Eric Aardoom, Paul Stravers:
An Application Specific Processor for a Multi-System Navigation Receiver. 128-131 - Ohad Falik, Gideon D. Intrater:
NSC's Digital Answering Machine Solution. 132-137 - Michael Butts, Jon Batcheller, Joseph Varghese:
An Efficient Logic Emulation System. 138-141
Panel Discussion
- James H. Aylor, Raul Camposano, Michael A. Schuette, Wayne H. Wolf, Nam Sung Woo:
The Future of Embedded System Design. 144-146
System Level Testing
- T. Okabayashi, K. Kubo, Z. Hirose, K. Suzuki:
System Level Verification of Large Scale Computer. 149-152
Logic Synthesis for FPGAs
- Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen:
An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. 154-158 - Shih-Chieh Chang, Malgorzata Marek-Sadowska:
Technology Mapping via Transformations of Function Graphs. 159-162 - T. Besson, H. Bouzouzou, M. Crastes, Ion Floricica, Gabriele Saucier:
Synthesis on Multiplexer-Based F.P.G.A. Using Binary Decision Diagrams. 163-167
Special Purpose Architectures
- Amar Mukherjee, Jeffrey W. Flieder, N. Ranganathan:
MARVLE: A VLSI Chip for Variable Length Encoding and Decoding. 170-173 - Baher Haroun, Elie Torbey:
Synthesis of Multiple Bus/Functional Unit Architectures Implementing Neural Networks. 174-178 - Gisela Mahlich, G.-H. Huaman-Bollo, Joachim Preißner, Johannes Schuck, Hans Sahm, P. Weingart, Dirk Weinsziehr, J. Yeandel:
One-Chip System Integration for GSM with the DSP KISS-16V2. 179-182
Interconnect
- Soo-Young Oh, Keh-Jeng Chang, Norman Chang, Ken Lee:
Interconnect Modeling and Design in High-Speed VLSI/ULSI Systems. 184-189 - C.-S. Li, Harold S. Stone, C. M. Olsen:
Fully Differential Optical Interconnects for High-Speed Digital Systems. 190-193 - Jay K. Adams, Donald E. Thomas:
Addressing the Tradeoff Between Standard and Custom ICs in System Level Design. 194-197
CPUs
- Charles R. Moore, D. M. Balser, John S. Muhich, R. E. East:
IBM Single Chip RISC Processor (RSC). 200-204 - Sanjay Desai:
The Architecture of the LR33020 GraphX Processor: A MIPS-RISC Based X-Terminal Controller. 205-208 - David May, Roger Shepherd, Peter Thompson:
The T9000 Transputer. 209-212
Interconnect Analysis
- Raj Mittra:
Electromagnetic Modeling and Simulation of Electronic Packages. 214-217 - Hansruedi Heeb, Albert E. Ruehli, J. Eric Bracken, Ronald A. Rohrer:
Three Dimensional Circuit Oriented Electromagnetic Modeling for VLSI Interconnects. 218-221 - Colin Gordon:
Time Domain Simulation of Multiconductor Transmission Lines with Frequency-Dependent Losses. 222-228
VLSI Technology /BiCMOS
- George A. Sai-Halasz:
Directions in Futrue High End Processors. 230-233 - Prasad Raje:
Design and Scaling of BiCMOS Circuits. 234-238
System Level Verification and Test
- Jeffrey I. Alter:
DACCT - Dynamic ACCess Testing of IBM Large Systems. 240-244 - Ashok K. Chandra, Vijay S. Iyengar:
Constraint Slving for Test Case Generation. 245-248 - Miyako Odawara, Kazunori Kuriyama, Tadaaki Bandoh:
Archimedes: An Approach to Architecutre-Independent Modeling for High-Level Simulation. 249-254
Issues in Built-in-Self-Test
- Chien-In Henry Chen, Joel T. Yuen:
Concurrent Test Scheduling in Built-In Self-Test Environment. 256-259 - Shujian Zhang, Rod Byrne, D. Michael Miller:
BIST Generators for Sequential Faults. 260-263 - Chien-In Henry Chen, Joel T. Yuen, Ji-Der Lee:
Autonomous-Tol for Hardware Partitioning in a Built-in Self-Test Environment. 264-267
Timed Asynchronous Circuits
- Jerry R. Burch:
Delay Models for Verifying Speed-Dependent Asynchronous Circuits. 270-274 - Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
Linear Programming for Optimum Hazard Elimination in Asynchronous Circuits. 275-278 - Chris J. Myers, Teresa H.-Y. Meng:
Synthesis of Timed Asynchronous Circuits. 279-284
Scheduling in High-Level Synthesis
- Alex Orailoglu, Ramesh Karri:
High-Level Synthesis of Self-Recovering MicroArchitectures. 286-289 - Minjoong Rim, Rajiv Jain:
Estimating Lower-Bound Performance of Schedules Using a Relaxation Technique. 290-294 - Karl van Rompaey, Ivo Bolsens, Hugo De Man:
Just in Time Scheduling. 295-300
Architecture, Verification, and CAD Strategy of the NVAX Chip
- Debra Bernstein, John F. Brown III, Rebecca L. Stamm, G. Michael Uhler:
NVAX and NVAX + Single-Chip CMOS VAX Microprocessors. 302-305 - Walker Anderson:
Logical Verification of the NVAX CPU Chip Design. 306-309 - Victor Peng, Dale R. Donchin, Yao-Tsung Yen:
Design Methodology and CAD Tools for the NVAX Microprocessor. 310-313
Sequential Synthesis
- James Pardey, Tomasz Kozlowski, Jonathan Saul, Martin Bolton:
State Assignment Algorithms for Parallel Controller Synthesis. 316-319 - Maya K. Yajnik, Maciej J. Ciesielski:
Finite State Machine Decomposition Using Multiway Partitioning. 320-323 - June-Kyung Rho, Fabio Somenzi:
The Role of Prime Compatibles in the Minimization of Finite State Machines. 324-327 - Ellen Sentovich, Kanwar Jit Singh, Cho W. Moon, Hamid Savoj, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Sequential Circuit Design Using Synthesis and Optimization. 328-333
Asynchronous Architectures
- Gernot Armin Liebchen, Ganesh Gopalakrishnan:
Dynamic Reordering of Hgh Latency Transactions Using a Modified a Micropipeline. 336-340 - Steven M. Nowick, Kenneth Y. Yun, David L. Dill:
Practical Asynchronous Controller Design. 341-345 - Kenneth Y. Yun, David L. Dill, Steven M. Nowick:
Synthesis of 3D Asynchronous State Machines. 346-350 - N. C. Paver, Paul Day, Stephen B. Furber, Jim D. Garside, John V. Woods:
Register Locking in an Asynchronous Microprocessor. 351-355
Test Generation and Fault Simulation
- Dimitrios Kagaris, Fillia Makedon, Spyros Tragoudas:
On Minimizing Hardware Overhead for Pseudoexhaustive Circuit Testability. 358-364 - Sami A. Al-Arian, Musaed A. Al-Kharji:
Fault Simulation and Test Generation by Fault Sampling Techniques. 365-368 - Niraj K. Jha, Sying-Jyan Wang, Phillip C. Gripka:
Multiple Input Bridging Fault Detection in CMOS Sequential Circuits. 369-372 - Ding Lu, Carol Q. Tong:
Multiple Fault Detection in CMOS Logic Circuits. 373-376
Floorplanning and Layout
- Yang Cai, D. F. Wong:
Channel Density Minimization by Pin Permutation. 378-382 - Yachyang Sun, C. L. Liu:
An Area Minimizer for Floorplans with L-Shaped Regions. 383-386 - Pradip Bose, David LaPotin, Gopalakrishnan Vijayan, Sungho Kim:
Workload-Driven Floorplanning for MIPS Optimization. 387-391
ICCD Banquet
- Nick Tredennick:
Desktop Wars - The PC Versus the Workstation. 394
Asynchronous Control Circuits
- Alexandre Yakovlev:
On Limitations and Extensions of STG Model for Designing Asynchronous Control Circuits. 396-400 - Shlomo Kipnis:
Analysis of Asynchronous Binary Arbitration on Digital-Transmission-Line Busses. 401-406 - Tam-Anh Chu:
Automatic Synthesis and Verification of Hazard-Free Control Circuits from Asynchronous Finite State Machine Specifications. 407-413
The Message Driven Processor
- William J. Dally, Andrew A. Chien, Stuart Fiske, Gregory A. Fyler, Waldemar Horwat, John S. Keen, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, D. Scott Wills:
The Message Driven Processor: An Integrated Multicomputer Processing Element. 416-419 - Peter R. Nuth, William J. Dally:
The J-Machine Network. 420-423 - Richard A. Lethin, William J. Dally:
MDP Design Tools and Methods. 424-428
Verification, Validation, and Test
- Margaret A. St. Pierre, Shaw-Wen Yang, Dan Cassiday:
Functional VLSI Design Verification Methodology for the CM-5 Massively Parallel Supercomputer. 430-435 - Robert C. Zak Jr., Jeffrey V. Hill:
An IEEE 1149.1 Compliant Testability Architecture with Internal Scan. 436-442 - Sungho Kang, Stephen A. Szygenda:
Modeling and Simulation of Design Errors. 443-446
Logic Synthesis I
- William K. C. Lam, Robert K. Brayton:
On Relationship Between ITE and BDD. 448-451 - Yung-Te Lai, Sarma Sastry, Massoud Pedram:
Boolean Matching Using Binary Decision Diagrams with Applications to Logic Synthesis and Verification. 452-458 - Mark A. Heap, William A. Rogers, M. Ray Mercer:
A Synthesis Algorithm for Two-Level XOR Based Circuits. 459-463
Logic Synthesis II
- Kaushik Roy, Sharat Prasad:
SYCLOP: Synthesis of CMOS Logic for Low Power Applications. 464-467 - Paul T. Gutwin, Patrick C. McGeer, Robert K. Brayton:
Delay Prediction for Technology-Independent Logic Equations. 468-471 - Ursula Westerholz, Heinrich Theodor Vierhaus:
Library Mapping of CMOS-Switch-Level-Circuits by Extraction of Isomorphic Subgraphs. 472-475
Design of Fault-Tolerant and Self-Checking Circuits
- Abhijit Chatterjee:
A New Approach to Fault-Tolerance in Linear Analog Systems Based on Checksum-Coded State Space Representations. 478-481 - Xiaodong Xie, Alexander Albicki, Andrzej Krasniewski:
Design of Robust-Path-Delay-Fault-Testable Combinational Circuits by Boolean Space Expansion. 482-485 - Zhi-Jian Jiang, R. Venkatesen:
Theory and Design of Two-Rail Totally Self-Checking Basic Building Blocks. 486-489
Special Purpose Systems
- Georges Quénot, Bertrand Y. Zavidovique:
The ETCA Data-Flow Functional Computer for Real-Time Image Processing. 492-495 - Barry S. Fagin, J. Gill Watt:
FPGA and Rapid Prototyping Technology Use in a Special Purpose Computer for Molecular Genetics. 496-501 - Smaragda Konstantinidou:
The Selective Extra-Stage Butterfly. 502-506
Circuit and Switch Level Simulation
- Sankaran Karthik, Jacob A. Abraham:
Distributed VLSI Simulation on a Network of Workstations. 508-511 - Jalal A. Wehbeh, Daniel G. Saab:
Hierarchical Simulation of MOS Circuits Using Extracted Functional Models. 512-515 - Bob Melville, Peter Feldmann, Shahriar Moinian:
AC++ Based Environment for Analog Circuit Simulation. 516-519
Formal Verification I
- David L. Dill, Andreas J. Drexler, Alan J. Hu, C. Han Yang:
Protocol Verification as a Hardware Design Aid. 522-525 - Eduard Cerny:
Verification of I/O Trace Set Inclusion for a Class of Non-Deterministic Finite State Machines. 526-530 - Andrew D. Gordon:
The Formal Definition of a Synchronous Hardware-Description Language in Higher Order Logic. 531-534
Environments for High-Level CAD
- Andreas Kuehlmann, Reinaldo A. Bergamaschi:
High-Level State Machine Specification and Synthesis. 536-539 - Atsushi Takahara:
Versioning and Concurrency Control in a Distributed Design Environment. 540-543 - Balkrishna Ramkumar, Prithviraj Banerjee:
ProperCAd: A Portable Object-Oriented Parallel Environment for VLSI CAD. 544-548
Memory Designs
- Lishing Liu, Jih-Kwon Peir:
Sampling of Cache Congruence Classes. 552-557 - Steve Nowakowski, Matthew T. O'Keefe:
A CRegs Implementation Study Based on the MIPS-X RISC Processor. 558-563 - H. Fatih Ugurdag, Christos A. Papachristou:
ALMP: A Shifting Memory Architecture for Loop Pipelining. 564-568
Self-Testing and Repair of Memories
- O. Kebichi, Michael Nicolaidis:
A Tool for Automatic Generation of BISTed and Transparent BISTed Rams. 570-575 - Tom Chen, Glen Sunada:
An Ultra-Large Capacity Single-Chip Memory Architecture With Self-Testing and Self-Repairing. 576-581 - Bapiraju Vinnakota, Jason Andrews:
Repair of RAMs With Clustered Faults. 582-585
Formal Verification II
- Timothy Kam, P. A. Subrahmanyam:
Comparing Layouts with HDL Models: A Formal Verification Technique. 588-591 - Masahiro Fujita:
RTL Design Verification by Making Use of Datapath Information. 592-597 - Prabhat Jain, Ganesh Gopalakrishnan:
Some Techniques for Efficient Symbolic Simulation-Based Verification. 598-602
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