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ORCIDShin'ichiro Mutoh
Person information
- affiliation: NTT Microsystem Integration Laboratories, Nippon Telegraph and Telephone Corporation, Atsugi, Japan
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2010 – 2019
- 2015
[c7]Chris Nicol, Shinichiro Mutoh:
Session 24 overview: Secure, efficient circuits for IoT: Technology directions subcommittee. ISSCC 2015: 426-427- 2013
- [c6]Fu-Lung Hsueh, Shinichiro Mutoh:
Session 11 overview: Emerging memory and wireless technology. ISSCC 2013: 190-191 - 2012
- [j9]Hiroshi Makino, Shunji Nakata
, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda:
Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield. IET Circuits Devices Syst. 6(4): 260-270 (2012) - [j8]Shunji Nakata, Ryota Honda, Hiroshi Makino, Shin'ichiro Mutoh, Masayuki Miyama, Yoshio Matsuda:
General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(10): 2301-2314 (2012) - 2011
- [j7]Mamoru Ugajin, Toshishige Shimamura, Shin'ichiro Mutoh, Mitsuru Harada:
Design and Performance of a Sub-Nano-Ampere Two-Stage Power Management Circuit in 0.35-µm CMOS for Dust-Size Sensor Nodes. IEICE Trans. Electron. 94-C(7): 1206-1211 (2011) - [j6]Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda:
Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution. IEEE Trans. Circuits Syst. II Express Briefs 58-II(4): 230-234 (2011) - 2010
- [j5]Shunji Nakata, Shin'ichiro Mutoh, Hiroshi Makino, Masayuki Miyama, Yoshio Matsuda:
Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipation. IEICE Electron. Express 7(9): 640-646 (2010) - [c5]Shunji Nakata, Hirotsugu Suzuki, Ryota Honda, Takahito Kusumoto, Shin'ichiro Mutoh, Hiroshi Makino, Masayuki Miyama, Yoshio Matsuda:
Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit. ISCAS 2010: 2474-2477 - [c4]Toshishige Shimamura, Mamoru Ugajin, Kenji Suzuki, Kazuyoshi Ono, Norio Sato, Kei Kuwabara, Hiroki Morimura, Shin'ichiro Mutoh:
Nano-watt power management and vibration sensing on a dust-size batteryless sensor node for ambient intelligence applications. ISSCC 2010: 504-505
2000 – 2009
- 2005
- [j4]Jun Terada, Yasuyuki Matsuya, Shin'ichiro Mutoh, Yuichi Kado:
A 1-V Cyclic A/D Converter Using FD-SOI Sample/Hold Circuits for Sensor Networks. IEICE Trans. Electron. 88-C(4): 479-483 (2005) - 2004
- [c3]Koji Fujii, Jun Terada, Junichi Kodate, Tsuneo Tsukahara, Shin'ichiro Mutoh, Yuichi Kado:
A 2-Mb/s, UHF-band, wireless sensor node for real-time multi-point sensing. ISCAS (4) 2004: 912-915 - 2003
- [c2]Eiichi Hosoya, Miki Kitabata, Hidenori Sato, Ikuo Harada, Hisao Nojima, Fumiharu Morisawa, Shinichiro Mutoh, Akira Onozawa:
A Mirror Metaphor Interaction System: Touching Remote Real Objects in an Augmented Reality Environment. ISMAR 2003: 350-351
1990 – 1999
- 1999
- [c1]Shinichiro Mutoh, Satoshi Shigematsu, Yoshinori Gotoh, Shinsuke Konaka:
Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs. ASP-DAC 1999: 113-116 - 1997
- [j3]Satoshi Shigematsu, Shin'ichiro Mutoh, Yasuyuki Matsuya, Yasuyuki Tanabe, Junzo Yamada:
A 1-V high-speed MTCMOS circuit scheme for power-down application circuits. IEEE J. Solid State Circuits 32(6): 861-869 (1997) - 1996
- [j2]Shinichiro Mutoh, Satoshi Shigematsu, Yasuyuki Matsuya, H. Fukuda, T. Kaneko, Junzo Yamada:
A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application. IEEE J. Solid State Circuits 31(11): 1795-1802 (1996) - 1995
- [j1]Shin'ichiro Mutoh, Takakuni Douseki, Yasuyuki Matsuya, Takahko Aoki, Satoshi Shigematsu, Junzo Yamada:
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS. IEEE J. Solid State Circuits 30(8): 847-854 (1995)
Coauthor Index
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