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ORCIDISSCC 2015: San Francisco, CA, USA
- 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015. IEEE 2015, ISBN 978-1-4799-6223-5
- Anantha P. Chandrakasan, Hoi-Jun Yoo:
Session 1 overview: Plenary session. 6-7 - Kinam Kim:
1.1 Silicon technologies and solutions for the data-driven world. 1-7 - Sehat Sutardja:
1.2 The future of IC design innovation. 1-6 - Willy Sansen:
1.3 Analog CMOS from 5 micrometer to 5 nanometer. 1-6 - Ehsan Afshari, Minoru Fujishima:
Session 2 Overview: RF TX/RX design techniques: RF subcommittee. 28-29 - Hao Wu, Mohyee Mikhemar, David Murphy, Hooman Darabi, Mau-Chung Frank Chang
:
2.1 A highly linear inductorless wideband receiver with phase- and thermal-noise cancellation. 1-3 - Barend van Liempd, Benjamin P. Hershberg, Kuba Raczkowski, Saneaki Ariumi, Udo Karthaus, Karl-Frederik Bink, Jan Craninckx:
2.2 A +70dBm IIP3 single-ended electrical-balance duplexer in 0.18um SOI CMOS. 1-3 - Fanyi Meng, Kaixue Ma, Kiat Seng Yeo:
2.3 A 130-to-180GHz 0.0035mm2 SPDT switch with 3.3dB loss and 23.7dB isolation in 65nm bulk CMOS. 1-3 - Zhicheng Lin, Pui-In Mak, Rui Paulo Martins:
2.4 A 0.028mm2 11mW single-mixing blocker-tolerant receiver with double-RF N-path filtering, S11 centering, +13dBm OB-IIP3 and 1.5-to-2.9dB NF. 1-3 - Wanxin Ye, Kaixue Ma, Kiat Seng Yeo:
2.5 A 2-to-6GHz Class-AB power amplifier with 28.4% PAE in 65nm CMOS supporting 256QAM. 1-3 - Ahmed Farouk Aref, Renato Negra, Muhammad Abdullah Khan:
2.6 Class-0: A highly linear class of power amplifiers in 0.13μm CMOS for WCDMA/LTE applications. 1-3 - Seung-Chul Lee, Ji-Seon Paek, Jun-Hee Jung, Yong-Sik Youn, Sung-Jun Lee, Min-Soo Cho, Jae-Jol Han, Jung-Hyun Choi, Yong-Whan Joo, Takahiro Nomiyama, Su-Ho Lee, Il-Young Sohn, Thomas Byunghak Cho, Byeong-Ha Park, Inyup Kang:
2.7 A hybrid supply modulator with 10dB ET operation dynamic range achieving a PAE of 42.6% at 27.0dBm PA output power. 1-3 - Song Hu, Shouhei Kousai, Hua Wang:
2.8 A broadband CMOS digital power amplifier with hybrid Class-G Doherty efficiency enhancement. 1-3 - Kunal Datta, Hossein Hashemi:
2.9 A 29dBm 18.5% peak PAE mm-Wave digital power amplifier with dynamic load modulation. 1-3 - Aurelien Larie, Eric Kerherve, Baudouin Martineau, Lionel Vogt, Didier Belot:
2.10 A 60GHz 28nm UTBB FD-SOI CMOS reconfigurable power amplifier with 21% PAE, 18.2dBm P1dB and 74mW PDC. 1-3 - Ken Chang, Shunichi Kaeriyama:
Session 3 overview: Ultra-high-speed wireline transceivers and energy-efficient links: Wireline subcommittee. 50-51 - Bo Zhang, Karapet Khanoyan, Hamid Hatamkhani, Haitao Tong, Kangmin Hu, Siavash Fallahi, Kambiz Vakilian, Anthony Brewster:
3.1 A 28Gb/s multi-standard serial-link transceiver for backplane applications in 28nm CMOS. 1-3 - Takashi Kawamoto, Takayasu Norimatsu, Kenji Kogo, Fumio Yuki, Norio Nakajima, Masatoshi Tsuge, Tatsunori Usugi, Tomofumi Hokari, Hideki Koba, Takemasa Komori, Junya Nasu, Tsuneo Kawamata, Yuichi Ito, Seiichi Umai, Jun Kumazawa, Hiroaki Kurahashi, Takashi Muto, Takeo Yamashita, Masatoshi Hasegawa, Keiichi Higeta:
3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS. 1-3 - Parag Upadhyaya, Jafar Savoj, Fu-Tai An, Ade Bekele, Anup P. Jose, Bruce Xu, Zhaoyin Daniel Wu, Didem Turker, Hesam Amir Aslanzadeh, Hiva Hedayati, Jay Im, Siok-Wei Lim, Stanley Chen, Toan Pham, Yohan Frans, Ken Chang:
3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS. 1-3 - Ali Nazemi, Kangmin Hu, Burak Çatli, Delong Cui, Ullas Singh, Tim He, Zhi Chao Huang, Bo Zhang, Afshin Momtaz, Jun Cao:
3.4 A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS. 1-3 - Jihwan Kim, Ajay Balankutty, Amr Elshazly, Yan-Yu Huang, Hang Song, Kai Yu, Frank O'Mahony:
3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS. 1-3 - Ayman Shafik, Ehsan Zhian Tabasy, Shengchang Cai, Keytaek Lee, Sebastian Hoyos, Samuel Palermo:
3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS. 1-3 - Tejasvi Anand, Mrunmay Talegaonkar, Ahmed Elkholy, Saurabh Saxena, Amr Elshazly, Pavan Kumar Hanumolu:
3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS. 1-3 - Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini, Pavan Kumar Hanumolu:
3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS. 1-3 - Atsuki Inoue, Jinuk Luke Shin:
Session 4 overview: Processors: High-performance digital subcommittee. 68-69 - James D. Warnock, Brian W. Curran, John Badar, Gregory Fredeman, Donald W. Plass, Yuen H. Chan, Sean M. Carey, Gerard Salem, Friedrich Schroeder, Frank Malgioglio, Guenter Mayer, Christopher J. Berry, Michael H. Wood, Yiu-Hing Chan, Mark D. Mayo, John Isakson, Charudhattan Nagarajan, Tobias Werner, Leon J. Sigal, Ricardo Nigaglioni, Mark Cichanowski, Jeffrey A. Zitz, Matthew M. Ziegler, Tim Bronson, Gerald Strevig, Daniel Dreps, Ruchir Puri, Douglas Malone, Dieter F. Wendel, Pak-kin Mak, Michael A. Blake:
4.1 22nm Next-generation IBM System z microprocessor. 1-3 - Penny Li, Jinuk Luke Shin, Georgios K. Konstadinidis, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister:
4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor. 1-3 - Venkatram Krishnaswamy, Jeffrey Brooks, Georgios K. Konstadinidis, Curtis McAllister, Ha Pham, Sebastian Turullols, Jinuk Luke Shin, Yifan YangGong, Haowei Zhang:
4.3 Fine-grained adaptive power management of the SPARC M7 processor. 1-3 - Ronald P. Luijten, Dae Pham, Rolf Clauberg, Matteo Cossale, Huy N. Nguyen, Mihir Pandya:
4.4 Energy-efficient microserver based on a 12-core 1.8GHz 188K-CoreMark 28nm bulk CMOS 64b SoC for big-data applications with 159GB/S/L memory bandwidth system density. 1-3 - William J. Bowhill, Blaine A. Stackhouse, Nevine Nassif, Zibing Yang, Arvind Raghavan, Charles Morganti, Chris Houghton, Dan Krueger, Olivier Franza, Jayen Desai, Jason Crop, Dave Bradley, Chris Bostak, Sal Bhimji, Matt Becker:
4.5 The Xeon® processor E5-2600 v3: A 22nm 18-core product family. 1-3 - Seongwook Park, Kyeongryeol Bong, Dongjoo Shin, Jinmook Lee, Sungpill Choi, Hoi-Jun Yoo:
4.6 A1.93TOPS/W scalable deep learning/inference processor with tetra-parallel MIMD architecture for big-data applications. 1-3 - Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De:
4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging. 1-3 - Kathryn Wilcox, David Akeson, Harry R. Fair III, Jim Farrell, Dave Johnson, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White:
4.8 A 28nm x86 APU optimized for power and area efficiency. 1-3 - Xicheng Jiang, Ed van Tuijl:
Session 5 overview: Analog techniques: Analog subcommittee. 86-87 - Yoshinori Kusuda:
5.1 A 60V auto-zero and chopper operational amplifier with 800kHz interleaved clocks and input bias-current trimming. 1-3 - Long Xu, Burak Gonen, Qinwen Fan, Johan H. Huijsing, Kofi A. A. Makinwa:
5.2 A 110dB SNR ADC with ±30V input common-mode range and 8μV Offset for current sensing applications. 1-3 - Yi-Lin Tsai, Feng-Wen Lee, Tzu-Ying Chen, Tsung-Hsien Lin:
5.3 A 2-channel -83.2dB crosstalk 0.061mm2 CCIA with an orthogonal frequency chopping technique. 1-3 - Aatmesh Shrivastava, Kyle Craig, Nathan E. Roberts, David D. Wentzloff, Benton H. Calhoun:
5.4 A 32nW bandgap reference voltage operational from 0.5V supply for ultra-low power systems. 1-3 - Joeri Lechevallier, Remko E. Struiksma, Hani Sherry, Andreia Cathelin, Eric A. M. Klumperink, Bram Nauta:
5.5 A forward-body-bias tuned 450MHz Gm-C 3rd-order low-pass filter in 28nm UTBB FD-SOI with >1dBVp IIP3 over a 0.7-to-1V supply. 1-3 - Saad Bin Nasir, Samantak Gangopadhyay, Arijit Raychowdhury:
5.6 A 0.13μm fully digital low-dropout regulator with adaptive control and reduced dynamic stability for ultra-wide dynamic range. 1-3 - Jongmi Lee, Youngwoo Ji, Seungnam Choi, Young-Chul Cho, Seong-Jin Jang, Joo-Sun Choi, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
5.7 A 29nW bandgap reference circuit. 1-3 - Gerhard Maderbacher, Stefano Marsili, Mario Motz, Thomas Jackum, Johannes Thielmann, Henrik Hassander, Herbert Gruber, Florian Hus, Christoph Sandner:
5.8 A digitally assisted single-point-calibration CMOS bandgap voltage reference with a 3σ inaccuracy of ±0.08% for fuel-gauge applications. 1-3 - Danielle Griffith, James Murdock, Per Torstein Røine, Thomas Murphy:
5.9 A 37μW dual-mode crystal oscillator for single-crystal radios. 1-3 - Junghyup Lee, Pyoungwon Park, SeongHwan Cho, Minkyu Je:
5.10 A 4.7MHz 53μW fully differential CMOS reference clock oscillator with -22dB worst-case PSNR for miniaturized SoCs. 1-3 - Yusuke Oike, Young-Sun Na:
Session 6 overview: Image sensors and displays: IMMD subcommittee. 108-109 - Atsushi Suzuki, Nobutaka Shimamura, Toshiki Kainuma, Naoki Kawazu, Chihiro Okada, Takumi Oka, Kensuke Koiso, Atsushi Masagaki, Yoichi Yagasaki, Shigeru Gonoi, Tatsuya Ichikawa, Masatoshi Mizuno, Tatsuya Sugioka, Takafumi Morikawa, Yoshiaki Inada, Hayato Wakabayashi:
6.1 A 1/1.7-inch 20Mpixel Back-illuminated stacked CMOS image sensor for new imaging applications. 1-3 - Ryohei Funatsu, Steven Huang, Takayuki Yamashita, Kevin Stevulak, Jeff Rysinski, David Estrada, Shi Yan, Takuji Soeno, Tomohiro Nakamura, Tetsuya Hayashida, Hiroshi Shimamoto, Barmak Mansoorian:
6.2 133Mpixel 60fps CMOS image sensor with 32-column shared high-speed column-parallel SAR ADCs. 1-3 - Jaehyuk Choi, Jungsoon Shin, Dongwu Kang, Du-Sik Park:
6.3 A 45.5μW 15fps always-on CMOS image sensor for mobile and wearable devices. 1-3 - Futa Mochizuki, Keiichiro Kagawa, Shin-ichiro Okihara, Min-Woong Seo, Bo Zhang, Taishi Takasawa, Keita Yasutomi, Shoji Kawahito:
6.4 Single-shot 200Mfps 5×3-aperture compressive CMOS imager. 1-3 - Takuro Ohmaru, Takashi Nakagawa, Shuhei Maeda, Yuki Okamoto, Munehiro Kozuma, Seiichi Yoneda, Hiroki Inoue, Yoshiyuki Kurokawa, Takayuki Ikeda, Yoshinori Ieda, Naoto Yamade, Hidekazu Miyairi, Makoto Ikeda, Shunpei Yamazaki:
6.5 25.3μW at 60fps 240×160-pixel vision sensor for motion capturing with in-pixel non-volatile analog memory using crystalline oxide semiconductor FET. 1-3 - Mutsumi Hamaguchi, Michiaki Takeda, Masayuki Miyamoto:
6.6 A 240Hz-reporting-rate mutual-capacitance touch-sensing analog front-end enabling multiple active/passive styluses with 41dB/32dB SNR for 0.5mm diameter. 1-3 - Li Du, Yan Zhang, Frank Hsiao, Adrian Tang, Yan Zhao, Yilei Li, Zuow-Zun Chen, Liting Huang, Mau-Chung Frank Chang:
6.7 A 2.3mW 11cm-range bootstrapped and correlated-double-sampling (BCDS) 3D touch sensor for mobile devices. 1-3 - Changbyung Park, Sungsoo Park, Kiduk Kim, Sang-Hui Park, Juwan Park, Yunhee Huh, Byunghoon Kang, Gyu-Hyeong Cho:
6.8 A pen-pressure-sensitive capacitive touch system using electrically coupled resonance pen. 1-3 - Fatih Hamzaoglu, Takashi Kono:
Session 7 overview: Non-volatile memory solutions: Memory subcommittee. 126-127 - Mario Sako, Yoshihisa Watanabe, Takao Nakajima, Jumpei Sato, Kazuyoshi Muraoka, Masaki Fujiu, Fumihiro Kouno, Michio Nakagawa, Masami Masuda, Koji Kato, Yuri Terada, Yuki Shimizu, Mitsuaki Honma, Akihiro Imamoto, Tomoko Araya, Hayato Konno, Takuya Okanaga, Tomofumi Fujimura, Xiaoqing Wang, Mai Muramoto, Masahiro Kamoshida, Masatoshi Kohno, Yoshinao Suzuki, Tomoharu Hashiguchi, Tsukasa Kobayashi, Masashi Yamaoka, Ryuji Yamashita:
7.1 A low-power 64Gb MLC NAND-flash memory in 15nm CMOS technology. 1-3 - Jae-Woo Im, Woopyo Jeong, Doo-Hyun Kim, Sangwan Nam, Dong-Kyo Shim, Myung-Hoon Choi, Hyun-Jun Yoon, Dae-Han Kim, Youse Kim, Hyun Wook Park, Dong-Hun Kwak, Sang-Won Park, Seok-Min Yoon, Wook-Ghee Hahn, Jinho Ryu, Sang-Won Shim, Kyung-Tae Kang, Sung-Ho Choi, Jeong-Don Ihm, Young-Sun Min, In-Mo Kim, Doosub Lee, Ji-Ho Cho, Ohsuk Kwon, Ji-Sang Lee, Moosung Kim, Sang-Hyun Joo, Jae-hoon Jang, Sang-Won Hwang, Dae-Seok Byeon, Hyang-Ja Yang, Ki-Tae Park, Kyehyun Kyung, Jeong-Hyuk Choi:
7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate. 1-3 - Yasuhiko Taito, Masaya Nakano, Hiromi Okimoto, Daisuke Okada, Takashi Ito, Takashi Kono, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi:
7.3 A 28nm embedded SG-MONOS flash macro for automotive achieving 200MHz read operation and 2.0MB/S write throughput at Ti, of 170°C. 1-3 - Chankyung Kim, Keewon Kwon, Chulwoo Park, Sungjin Jang, Joosun Choi:
7.4 A covalent-bonded cross-coupled current-mode sense amplifier for STT-MRAM with 1T1MTJ common source-line structure array. 1-3 - Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita:
7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture. 1-3 - Hyun-Jin Kim, Jeong-Don Lim, Jang-Woo Lee, Dae-Hoon Na, Joon-Ho Shin, Chae-Hoon Kim, Seungwoo Yu, Ji-Yeon Shin, Seon-Kyoo Lee, Devraj Rajagopal, Sang-Tae Kim, Kyeong-Tae Kang, Jeong-Joon Park, Yongjin Kwon, Min-Jae Lee, Sunghoon Kim, Seunghoon Shin, Hyunggon Kim, Jin-Tae Kim, Ki-Sung Kim, Han-Sung Joo, Chanjin Park, Jae-Hwan Kim, Man-Joong Lee, Do-Kook Kim, Hyang-Ja Yang, Dae-Seok Byeon, Ki-Tae Park, Kyehyun Kyung, Jeong-Hyuk Choi:
7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip. 1-3 - Tsukasa Tokutomi, Masafumi Doi, Shogo Hachiya, Atsuro Kobayashi, Shuhei Tanakamaru, Ken Takeuchi:
7.7 Enterprise-grade 6x fast read and 5x highly reliable SSD with TLC NAND-flash memory for big-data storage. 1-3 - Victor V. Zyuban, Peter Nilsson:
Session 8 overview: Low-power digital techniques: Energy-efficient digital. 142-143 - James Myers, Anand Savanth, David Howard, Rohan Gaddh, Pranay Prabhat, David Flynn:
8.1 An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65nm CMOS for WSN applications. 1-3 - Wootaek Lim, Inhee Lee, Dennis Sylvester, David T. Blaauw:
8.2 Batteryless Sub-nW Cortex-M0+ processor with dynamic leakage-suppression logic. 1-3 - Vipul Kumar Singhal, Vinod Menezes, Srinivasa Chakravarthy, Mahesh Mehendale:
8.3 A 10.5μA/MHz at 16MHz single-cycle non-volatile memory access microcontroller with full state retention at 108nA in a 90nm process. 1-3 - Sylvain Clerc, Mehdi Saligane, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Cyril Bottoni, David Bol, Julien De Vos, Dominique Zamora, Benjamin Coeffic, Dimitri Soussan, Damien Croain, Mehdi Naceur, Pierre Schamberger, Philippe Roche, Dennis Sylvester:
8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. 1-3 - Keith A. Bowman, Sarthak Raina, Todd Bridges, Daniel Yingling, Hoan Nguyen, Brad Appel, Yesh Kolla, Jihoon Jeong, Francois Atallah, David Hansquine:
8.5 A 16nm auto-calibrating dynamically adaptive clock distribution for maximizing supply-voltage-droop tolerance across a wide operating range. 1-3 - Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation. 1-3 - Kosta Luria, Joseph Shor, Michael Zelikson, Alex Lyakhov:
8.7 Dual-use low-drop-out regulator/power gate with linear and on-off conduction modes for microprocessor on-die supply voltages in 14nm. 1-3 - Li Lin, Chun-Huat Heng:
Session 9 overview: High-performance wireless: Wireless subcommittee. 158-159 - Theodore Georgantas, Kostis Vavelidis, Nikos Haralabidis, Stamatis Bouras, Iason Vassiliou, Charalampos Kapnistis, Yiannis Kokolakis, Hamed Peyravi, Gerasimos Theodoratos, Konstantinos S. Vryssas, Nikos Kanakaris, Christos Kokozidis, Spyros Kavvadias, Sofoklis Plevridis, Paul Mudge, Igor Elgorriaga, Aris Kyranas, Spyridon Liolis, Eleni Kytonaki, Giorgos Konstantopoulos, Pavlos Robogiannakis, Kosmas Tsilipanos, Michael Margaras, Panagiotis Betzios, Rahul Magoon, Nias Bouras, Maryam Rofougaran, Reza Rofougaran:
9.1 A 13mm2 40nm multiband GSM/EDGE/HSPA+/TDSCDMA/LTE transceiver. 1-3 - José Moreira, Stephan Leuschner, Nenad Stevanovic, Harald Pretl, Peter Pfann, Ronald Thüringer, Martin Kastner, Christian Proll, Andreas Schwarz, Florian Mrugalla, Jimena Saporiti, Umut Basaran, Andreas Langer, Tobias D. Werth, Timo Gossmann, Boris Kapfelsperger, Johann Pletzer:
9.2 A single-chip HSPA transceiver with fully integrated 3G CMOS power amplifiers. 1-3 - Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx:
9.3 A transmitter with 10b 128MS/S incremental-charge-based DAC achieving -155dBc/Hz out-of-band noise. 1-3 - Xiang Gao, Luns Tee, Wanghua Wu, Kun-Seok Lee, Arvind Anumula Paramanandam, Anuranjan Jha, Norman Liu, Edwin Chan, Li Lin:
9.4 A 28nm CMOS digital fractional-N PLL with -245.5dB FOM and a frequency tripler for 802.11abgn/ac radio. 1-3 - Hadong Jin, Dongsu Kim, Sangsu Jin, Hankyu Lee, Kyunghoon Moon, Huijung Kim, Bumman Kim:
9.5 efficient digital quadrature transmitter based on IQ cell sharing. 1-3 - Elbert Bechthum, Georgi I. Radulov, Joost Briaire, Govert Geelen, Arthur H. M. van Roermund:
9.6 A 5.3GHz 16b 1.75GS/S wideband RF Mixing-DAC achieving IMD<-82dBc up to 1.9GHz. 1-3 - Yen-Horng Chen, Neric Fong, Bing Xu, Caiyi Wang:
9.7 An LTE SAW-less transmitter using 33% duty-cycle LO signals for harmonic suppression. 1-3 - Gerrit den Besten, Ajith Amerasekera:
Session 10 overview: Advanced wireline techniques and PLLs: Wireline subcommittee. 174-175 - Atsutake Kosuge, Shu Ishizuka, Junichiro Kadomoto, Tadahiro Kuroda:
10.1 A 6Gb/s 6pJ/b 5mm-distance non-contact interface for modular smartphones using two-fold transmission-line coupler and EMC-qualified pulse transceiver. 1-3 - Wouter Volkaerts, Niels Van Thienen, Patrick Reynaert:
10.2 An FSK plastic waveguide communication link in 40nm CMOS. 1-3 - Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici:
10.3 A 7.5mW 7.5Gb/s mixed NRZ/multi-tone serial-data transceiver for multi-drop memory interfaces in 40nm CMOS. 1-3 - Hyun-Wook Lim, Sung-Won Choi, Sang-Kyu Lee, Chang-Hoon Baek, Jae-Youl Lee, Gyoo-Cheol Hwang, Bai-Sun Kong, Young-Hyun Jun:
10.4 A 5.8Gb/s adaptive integrating duobinary-based DFE receiver for multi-drop memory interface. 1-3 - Rajeev K. Dokania, Alexandra M. Kern, Mike He, Adam C. Faust, Richard Tseng, Skyler Weaver, Kai Yu, Christiaan Bil, Tao Liang, Frank O'Mahony:
10.5 A 5.9pJ/b 10Gb/s serial link with unequalized MM-CDR in 14nm tri-gate CMOS. 1-3 - Pier Andrea Francese, Thomas Toifl, Matthias Braendli, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel, Alessandro Cevrero, Danny Luu:
10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver. 1-3 - Ahmed Elkholy, Mrunmay Talegaonkar, Tejasvi Anand, Pavan Kumar Hanumolu:
10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS. 1-3 - Che-Fu Liang, Ping-Ying Wang:
10.8 A wideband fractional-N ring PLL using a near-ground pre-distorted switched-capacitor loop filter. 1-3 - Mark A. Ferriss, Bodhisatwa Sadhu, Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman:
10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme. 1-3 - Sam Kavusi, Makoto Ikeda:
Session 11 overview: Sensors and imagers for life sciences: IMMD subcommittee. 194-195 - JongKwan Choi, Jae-Myoung Kim, Gunpil Hwang, Jaehyeok Yang, MinGyu Choi, Hyeon-Min Bae:
11.1 A time-divided spread-spectrum code based 15pW-detectable multi-channel fNIRS IC for portable functional brain imaging. 1-3 - Min-Woong Seo, Keiichiro Kagawa, Keita Yasutomi, Taishi Takasawa, Yoshimasa Kawata, Nobukazu Teranishi, Zhuo Li, Izhal Abdul Halin, Shoji Kawahito:
11.2 A 10.8ps-time-resolution 256×512 image sensor with 2-Tap true-CDS lock-in pixels for fluorescence lifetime imaging. 1-3 - Matteo Perenzoni, Nicola Massari, Daniele Perenzoni, Leonardo Gasparini, David Stoppa:
11.3 A 160×120-pixel analog-counting single-photon imager with Sub-ns time-gating and self-referenced column-parallel A/D conversion for fluorescence lifetime imaging. 1-3 - Augusto Carimatto, Shingo Mandai, Esteban Venialgo, Ting Gong, Giacomo Borghi, Dennis R. Schaart, Edoardo Charbon:
11.4 A 67, 392-SPAD PVTB-compensated multi-channel digital SiPM with 432 column-parallel 48ps 17b TDCs for endoscopic time-of-flight PET. 1-3 - Neale A. W. Dutton, Salvatore Gnecchi, Luca Parmesan, Andrew J. Holmes, Bruce Rae, Lindsay A. Grant, Robert K. Henderson:
11.5 A time-correlated single-photon-counting sensor with 14GS/S histogramming time-to-digital converter. 1-3 - Kian Ann Ng, Yong Ping Xu:
11.6 A multi-channel neural-recording amplifier system with 90dB CMRR employing CMOS-inverter-based OTAs with CMFB through supply rails in 65nm CMOS. 1-3 - Jong Seok Park, Taiyun Chi, Jessica Butts, Tracy Hookway, Todd C. McDevitt, Hua Wang:
11.7 A multimodality CMOS sensor array for cell-based assay and drug screening. 1-3 - Hao-Yen Tang, Yipeng Lu, Stephanie Fung, David A. Horsley, Bernhard E. Boser:
11.8 Integrated ultrasonic system for measuring body-fat composition. 1-3 - Makato Takamiya, Dragan Maksimovic:
Session 12 overview: Inductor-based power conversion: Analog subcommittee. 212-213 - Sang-Han Lee, Jun-Suk Bang, Kye-Seok Yoon, Sung-Wan Hong, Changsik Shin, Min-Yong Jung, Gyu-Hyeong Cho:
12.1 A 0.518mm2 quasi-current-mode hysteretic buck DC-DC converter with 3μs load transient response in 0.35μm BCDMOS. 1-3 - Seong Joong Kim, Romesh Kumar Nandwana, Qadeer Ahmad Khan, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu:
12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm2 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS. 1-3 - Sung-Yun Park, Jihyun Cho, Kyuseok Lee, Euisik Yoon:
12.3 PWM buck converter with >80% PCE in 45μA-to-4mA loads using analog-digital hybrid control for impiantale biomedical systems. 1-3 - Stefan Dietrich, Sebastian Strache, Bastian Mohr, Jan Henning Mueller, Leo Rolff, Ralf Wunderlich, Stefan Heinen:
12.4 A 7.5W-output-power 96%-efficiency capacitor-free single-inductor 4-channel all-digital integrated DC-DC LED driver in a 0.18μm technology. 1-3 - Min-Yong Jung, Sang-Hui Park, Jun-Suk Bang, Dong-Chul Park, Se-un Shin, Gyu-Hyeong Cho:
12.5 An error-based controlled single-inductor 10-output DC-DC buck converter with high efficiency at light load using adaptive pulse modulation. 1-3 - Yi-Ping Su, Chiun-He Lin, Shen-Yu Peng, Ru-Yu Huang, Te-Fu Yang, Shin-Hao Chen, Ting-Jung Lo, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Chao-Cheng Lee, Jian-Ru Lin, Tsung-Yen Tsai:
12.6 90% Peak efficiency single-inductor-multiple-output DC-DC buck converter with output independent gate drive control. 1-3 - Mehdi Kiani, Byunghun Lee, Pyungwoo Yeon, Maysam Ghovanloo:
12.7 A power-management ASIC with Q-modulation capability for efficient inductive power transmission. 1-3 - Xing Li, Chi-Ying Tsui, Wing-Hung Ki:
12.8 Wireless power transfer system using primary equalizer for coupling- and load-range extension in bio-implant applications. 1-3 - Kyung-Goo Moti, Filippo Neri, Sungwoo Moon, Pyeongwoo Yeon, Jinhyuck Yu, Youso Cheon, Yong-Seong Roh, Myeonglyong Ko, Byeong-Ha Park:
12.9 A fully integrated 6W wireless power receiver operating at 6.78MHz with magnetic resonance coupling. 1-3 - Ali Afsahi, Jan van Sinderen:
Session 13 overview: Energy-efficient RF systems: RF & wireless subcommittees. 232-233 - Jae-Seung Lee, Joo-Myoung Kim, Jaesup Lee, Seok-Kyun Han, Sang-Gug Lee:
13.1 A 227pJ/b -83dBm 2.4GHz multi-channel OOK receiver adopting receiver-based FLL. 1-3