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ORCIDShunsuke Okura
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2020 – today
- 2024
[j17]Tatsuya Oyama, Kota Yoshida, Shunsuke Okura, Takeshi Fujino:
Adversarial Examples Created by Fault Injection Attack on Image Sensor Interface. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(3): 344-354 (2024)- 2023
- [j16]Ai Otani
, Hiroaki Ogawa, Ken Miyauchi, Sangman Han, Hideki Owada, Isao Takayanagi, Shunsuke Okura:
An Area-Efficient up/down Double-Sampling Circuit for a LOFIC CMOS Image Sensor. Sensors 23(9): 4478 (2023) - [j15]Tatsuya Oyama, Shunsuke Okura, Kota Yoshida, Takeshi Fujino:
Backdoor Attack on Deep Neural Networks Triggered by Fault Injection Attack on Image Sensor Interface. Sensors 23(10): 4742 (2023) - 2022
- [j14]Tatsuya Oyama, Shunsuke Okura, Kota Yoshida, Takeshi Fujino:
Experimental Study of Fault Injection Attack on Image Sensor Interface for Triggering Backdoored DNN Models. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(3): 336-343 (2022) - [c6]Tatsuya Oyama, Kota Yoshida, Shunsuke Okura, Takeshi Fujino:
Fundamental Study of Adversarial Examples Created by Fault Injection Attack on Image Sensor Interface. AsianHOST 2022: 1-6 - 2021
- [j13]Hiroshi Yamada, Shunsuke Okura, Masayoshi Shirahata, Takeshi Fujino:
Modeling attacks against device authentication using CMOS image sensor PUF. IEICE Electron. Express 18(7): 20210058 (2021) - [j12]Kota Yoshida, Mitsuru Shiozaki, Shunsuke Okura, Takaya Kubota, Takeshi Fujino:
Model Reverse-Engineering Attack against Systolic-Array-Based DNN Accelerator Using Correlation Power Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(1): 152-161 (2021) - [j11]Shunsuke Okura, Masanori Aoki, Tatsuya Oyama, Masayoshi Shirahata, Takeshi Fujino, Kenichiro Ishikawa, Isao Takayanagi:
Area-Efficient Post-Processing Circuits for Physically Unclonable Function with 2-Mpixel CMOS Image Sensor. Sensors 21(18): 6079 (2021) - [c5]Tatsuya Oyama, Shunsuke Okura, Kota Yoshida, Takeshi Fujino:
Backdoor Attack on Deep Neural Networks Triggered by Fault Injection Attack on Image Sensor Interface. ASHES@CCS 2021: 63-72 - 2020
- [c4]Kota Yoshida, Takaya Kubota, Shunsuke Okura, Mitsuru Shiozaki, Takeshi Fujino:
Model Reverse-Engineering Attack using Correlation Power Analysis against Systolic Array Based Neural Network Accelerator. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j10]Isao Takayanagi, Ken Miyauchi, Shunsuke Okura, Kazuya Mori, Junichi Nakamura, Shigetoshi Sugawa:
A 120-ke- Full-Well Capacity 160-µV/e- Conversion Gain 2.8-µm Backside-Illuminated Pixel with a Lateral Overflow Integration Capacitor. Sensors 19(24): 5572 (2019) - 2018
- [j9]Isao Takayanagi, Norio Yoshimura, Kazuya Mori, Shinichiro Matsuo, Shunsuke Tanaka, Hirofumi Abe, Naoto Yasuda, Kenichiro Ishikawa, Shunsuke Okura, Shinji Ohsawa, Toshinori Otaka:
An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process. Sensors 18(1): 203 (2018) - [c3]Shunsuke Okura, Ryota Ishiki, Masayoshi Shirahata, Takaya Kubota, Mitsuru Shiozaki, Kenichiro Ishikawa, Isao Takayanagi, Takeshi Fujino:
A Dynamic Soft-Decision Fuzzy Extractor for a CMOS Image Sensor PUF. ISPACS 2018: 54-59 - 2015
- [j8]Shunsuke Okura, Osamu Nishikido, Yusuke Sadanaga, Yasuhiro Kosaka, Norihiko Araki, Kazuhiro Ueda, Fukashi Morishita:
A 3.7 M-Pixel 1300-fps CMOS Image Sensor With 5.0 G-Pixel/s High-Speed Readout Circuit. IEEE J. Solid State Circuits 50(4): 1016-1024 (2015) - 2014
- [c2]Shunsuke Okura, Osamu Nishikido, Yusuke Sadanaga, Yasuhiro Kosaka, Norihiko Araki, Kazuhiro Ueda, Masanori Tachibana, Fukashi Morishita:
A 3.7M-pixel 1300-fps CMOS image sensor with 5.0G-pixel/s high-speed readout circuit. VLSIC 2014: 1-2 - 2013
- [j7]Tetsuro Okura, Shunsuke Okura, Toshimasa Matsuoka, Kenji Taniguchi:
A low-power technique for pipelined ADCs with programmable gain amplification. IEICE Electron. Express 10(1): 20120876 (2013) - [j6]Kazuhiro Ueda, Fukashi Morishita, Shunsuke Okura, Leona Okamura, Tsutomu Yoshihara, Kazutami Arimoto:
Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System. IEEE J. Solid State Circuits 48(11): 2608-2617 (2013) - 2011
- [j5]Indika U. K. Bogoda Appuhamylage, Shunsuke Okura, Toru Ido, Kenji Taniguchi:
An Area-Efficient, Low-Power CMOS Fractional Bandgap Reference. IEICE Trans. Electron. 94-C(6): 960-967 (2011) - 2010
- [j4]Indika U. K. Bogoda Appuhamylage, Shunsuke Okura, Toru Ido, Kenji Taniguchi:
An Area-Efficient CMOS Bandgap Reference Utilizing a Switched-Current Technique. IEEE Trans. Circuits Syst. II Express Briefs 57-II(10): 762-766 (2010) - [j3]Shunsuke Okura, Hajime Shibata, Tetsuro Okura, Toru Ido, Kenji Taniguchi:
A Frequency Model of a Continuously Driven Clocked CMOS Comparator. IEEE Trans. Circuits Syst. II Express Briefs 57-II(12): 956-960 (2010)
2000 – 2009
- 2009
- [j2]Shunsuke Okura, Tetsuro Okura, Toru Ido, Kenji Taniguchi:
A Reference Voltage Buffer with Settling Boost Technique for a 12 bit 18 MHz Multibit/Stage Pipelined A/D Converter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(2): 367-373 (2009) - 2007
- [j1]Shunsuke Okura, Tetsuro Okura, Indika U. K. Bogoda Appuhamylage, Kenji Taniguchi:
A 10-bit 800-Column Low-Power RAM Bank Including Energy-Efficient D-Flip-Flops for a Column-Parallel ADC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(2): 358-364 (2007) - 2006
- [c1]Shunsuke Okura, Tetsuro Okura, Kenji Taniguchi, Hajime Shibata:
Frequency Response Analysis of Latch Utilized in High-Speed Comparator. ICECS 2006: 1077-1080
Coauthor Index
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