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2020 – today
- 2023
[j8]Hiroyuki Uzawa, Shuhei Yoshida, Yukou Iinuma, Saki Hatta, Daisuke Kobayashi, Yuya Omori, Yusuke Horishita, Ken Nakamura, Shuichi Takada, Hassan Toorabally, Koyo Nitta
, Koji Yamazaki, Kimikazu Sano:
High-definition technology of AI inference scheme for object detection on edge/terminal. IEICE Electron. Express 20(13): 20232002 (2023)- [c20]Natsuki Ota, Toshinori Hosokawa, Koji Yamazaki, Yukari Yamauchi, Masayuki Arai:
An Estimation Method of Defect Types Using Artificial Neural Networks and Fault Detection Information. DFT 2023: 1-6 - 2021
- [c19]Kaori Fujinami, Tomoko Naganuma, Yushin Shinoda, Koji Yamazaki, Shinsuke Koike:
Attempts Toward Behavior Recognition of the Asian Black Bears Using an Accelerometer. ABC 2021: 57-79 - 2020
- [j7]Yuta Ukon, Koji Yamazaki, Koyo Nitta:
Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture. IEICE Trans. Commun. 103-B(1): 11-19 (2020)
2010 – 2019
- 2018
- [c18]Koji Yamazaki, Yuta Ukon, Shuhei Yoshida, Saki Hatta, Yusuke Sekihara, Shoko Ohteru, Tomoaki Kawamura, Takahiro Hatano, Koyo Nitta, Akihiko Miyazaki:
Flow Cache Cleansing with FPGA Hash Pipe for Highly Stabilized Software Data Plane. HPSR 2018: 1-6 - [c17]Yuta Ukon, Koji Yamazaki, Koyo Nitta:
Video Service Function Chaining with a Real-time Packet Reordering Circuit. ISCAS 2018: 1-5 - 2017
- [c16]Toshinori Hosokawa, Hideyuki Takano, Hiroshi Yamazaki, Koji Yamazaki:
A Diagnostic Fault Simulation Method for a Single Universal Logical Fault Model. PRDC 2017: 217-218 - 2015
- [c15]Koji Yamazaki, Yoshihiro Nakajima, Takahiro Hatano, Akihiko Miyazaki:
Lagopus FPGA - A reprogrammable data plane for high-performance software SDN switches. Hot Chips Symposium 2015: 1 - 2014
- [c14]Satoshi Sakurai, Koji Yamazaki, Tatsuo Ushiki, Futoshi Iwata:
Development of a single cell electroporation method using a scanning ion conductance microscope with a theta type probe pipette. MHS 2014: 1-5 - [c13]Koji Yamazaki, Takeshi Osaka, Sadayuki Yasuda, Shoko Ohteru, Akihiko Miyazaki:
Accelerating SDN/NFV with Transparent Offloading Architecture. ONS 2014 - 2013
- [j6]Sadayuki Yasuda, Shoko Ohteru, Yasuyuki Itoh, Koji Yamazaki, Yusuke Sekihara, Takashi Aoki, Masami Urano, Tsugumichi Shibata:
A reliable procedure in a new power management technique for a 200-Gbps packet forwarding LSI. IEICE Electron. Express 10(11): 20130231 (2013) - [c12]Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Hironobu Yotsuyanagi, Masaki Hashizume, Kewal K. Saluja:
Diagnosing Resistive Open Faults Using Small Delay Fault Simulation. Asian Test Symposium 2013: 79-84 - 2011
- [c11]Koji Yamazaki, Yusuke Sekihara, Takashi Aoki, Eiichi Hosoya, Akira Onozawa:
A heuristic algorithm for reducing system-level test vectors with high branch coverage. ISCAS 2011: 1475-1478 - 2010
- [c10]Masayoshi Yoshimura, Hiroshi Ogawa, Toshinori Hosokawa, Koji Yamazaki:
Evaluation of transition untestable faults using a multi-cycle capture test generation method. DDECS 2010: 273-276
2000 – 2009
- 2009
- [c9]Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume:
New Class of Tests for Open Faults with Considering Adjacent Lines. Asian Test Symposium 2009: 301-306 - [c8]Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume:
A Novel Approach for Improving the Quality of Open Fault Diagnosis. VLSI Design 2009: 85-90 - [c7]Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu:
Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC. VLSI Design 2009: 91-96 - 2008
- [j5]Koji Yamazaki, Yuzo Takamatsu:
A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information. IEICE Trans. Inf. Syst. 91-D(3): 661-666 (2008) - [j4]Yuzo Takamatsu, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Koji Yamazaki:
Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information. IEICE Trans. Inf. Syst. 91-D(3): 675-682 (2008) - [j3]Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato:
Post-BIST Fault Diagnosis for Multiple Faults. IEICE Trans. Inf. Syst. 91-D(3): 771-775 (2008) - 2007
- [c6]Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Takashi Aikyo, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume:
Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines. ATS 2007: 39-44 - 2006
- [c5]Koji Yamazaki, Yuzo Takamatsu:
Fanout-based fault diagnosis for open faults on pass/fail information. ATS 2006: 349-353 - [c4]Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato:
Effective Post-BIST Fault Diagnosis for Multiple Faults. DFT 2006: 401-109
1990 – 1999
- 1999
- [c3]Teruhiko Yamada, Toshinori Kotake, Hiroshi Takahashi, Koji Yamazaki:
Identification of Redundant Crosspoint Faults in Sequential PLAs with Fault-Free Hardware Reset. Asian Test Symposium 1999: 269-274 - 1997
- [c2]Koji Yamazaki, Teruhiko Yamada:
An approach to diagnose logical faults in partially observable sequential circuits. Asian Test Symposium 1997: 168-173 - 1995
- [j2]Koji Yamazaki, Teruhiko Yamada:
A Single Bridging Fault Location Technique for CMOS Combinational Circuits. IEICE Trans. Inf. Syst. 78-D(7): 817-821 (1995) - [c1]Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey:
A simple technique for locating gate-level faults in combinational circuits. Asian Test Symposium 1995: 65-70 - 1991
- [j1]Teruhiko Yamada, Koji Yamazaki:
Method of diagnosing single bridging faults in combinational circuit. Syst. Comput. Jpn. 22(9): 43-51 (1991)
Coauthor Index
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