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Toshinori Hosokawa
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2020 – today
- 2024
- [j8]Masayoshi Yoshimura, Atsuya Tsujikawa, Toshinori Hosokawa:
CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(3): 583-591 (2024) - 2023
- [c44]Toshinori Hosokawa, Kyohei Iizuka, Masayoshi Yoshimura:
An Evaluation of a Testability Measure for State Assignment to Estimate Transition Fault Coverage for Controllers. DFT 2023: 1-6 - [c43]Momona Mizota, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai:
A Block Partitioning Method for Region Exhaustive Test to Reduce the Number of Test Patterns and Improve Gate Exhaustive Fault Coverage. DFT 2023: 1-6 - [c42]Natsuki Ota, Toshinori Hosokawa, Koji Yamazaki, Yukari Yamauchi, Masayuki Arai:
An Estimation Method of Defect Types Using Artificial Neural Networks and Fault Detection Information. DFT 2023: 1-6 - [c41]Yudai Toyooka, Haruki Watanabe, Toshinori Hosokawa, Masayoshi Yoshimura:
An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing. DFT 2023: 1-6 - 2022
- [c40]Masayoshi Yoshimura, Atsuya Tsujikawa, Hiroshi Yamazaki, Toshinori Hosokawa:
CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level. DFT 2022: 1-6 - 2020
- [j7]Hideo Fujiwara, Katsuya Fujiwara, Toshinori Hosokawa:
Universal Testing for Linear Feed-Forward/Feedback Shift Registers. IEICE Trans. Inf. Syst. 103-D(5): 1023-1030 (2020) - [c39]Ryuki Asami, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai:
A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the Number of Test Patterns Using Partial MaxSAT. DFT 2020: 1-6 - [c38]Toshinori Hosokawa, Kenichiro Misawa, Hiroshi Yamazaki, Masayoshi Yoshimura, Masayuki Arai:
A Low Capture Power Oriented X-Identification-Filling Co-Optimization Method. IOLTS 2020: 1-4 - [c37]Yuki Ikegaya, Toshinori Hosokawa, Yuta Ishiyama, Hiroshi Yamazaki:
A Test Sensitization State Compaction Method on Controller Augmentation. IOLTS 2020: 1-6
2010 – 2019
- 2019
- [c36]Toshinori Hosokawa, Hiroshi Yamazaki, Kenichiro Misawa, Masayoshi Yoshimura, Yuki Hirama, Masavuki Arai:
A Low Capture Power Oriented X-filling Method Using Partial MaxSAT Iteratively. DFT 2019: 1-6 - [c35]Masayoshi Yoshimura, Yuki Takeuchi, Hiroshi Yamazaki, Toshinori Hosokawa:
A State Assignment Method to Improve Transition Fault Coverage for Controllers. DFT 2019: 1-4 - [c34]Yuta Ishiyama, Toshinori Hosokawa, Hiroshi Yamazaki:
A Design for Testability Method for k-Cycle Capture Test Generation. IOLTS 2019: 40-43 - [c33]Yuya Kinoshita, Toshinori Hosokawa, Hideo Fujiwara:
A Test Generation Method Based on k-Cycle Testing for Finite State Machines. IOLTS 2019: 232-235 - [c32]Yuki Takeuchi, Toshinori Hosokawa, Hiroshi Yamazaki, Masayoshi Yoshimura:
A Controller Augmentation Method to Improve Transition Fault Coverage for RTL Data-Paths. IOLTS 2019: 293-298 - 2018
- [c31]Toshinori Hosokawa, Morito Niseki, Masayoshi Yoshimura, Hiroshi Yamazaki, Masayuki Arai, Hiroyuki Yotsuyanagi, Masaki Hashizume:
A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification. IOLTS 2018: 43-46 - [c30]Sayuri Ochi, Hiroshi Yamazaki, Toshinori Hosokawa, Masayoshi Yoshimura:
A Capture Safe Static Test Compaction Method Based on Don't Cares. IOLTS 2018: 195-200 - [c29]Toshinori Hosokawa, Hiroshi Yamazaki, Shun Takeda, Masayoshi Yoshimura:
A Test Register Assignment Method Based on Controller Augmentation to Reduce the Number of Test Patterns. IOLTS 2018: 228-231 - 2017
- [j6]Toshinori Hosokawa, Atsushi Hirai, Yukari Yamauchi, Masayuki Arai:
A Low Capture Power Test Generation Method Based on Capture Safe Test Vector Manipulation. IEICE Trans. Inf. Syst. 100-D(9): 2118-2125 (2017) - [j5]Masayoshi Yoshimura, Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa:
A Don't Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2824-2833 (2017) - [c28]Toshinori Hosokawa, Atsushi Hirai, Hiroshi Yamazaki, Masayuki Arai:
A dynamic test compaction method on low power test generation based on capture safe test vectors. DFT 2017: 1-6 - [c27]Toshinori Hosokawa, Shun Takeda, Hiroshi Yamazaki, Masayoshi Yoshimura:
Controller augmentation and test point insertion at RTL for concurrent operational unit testing. IOLTS 2017: 17-20 - [c26]Toshinori Hosokawa, Hideyuki Takano, Hiroshi Yamazaki, Koji Yamazaki:
A Diagnostic Fault Simulation Method for a Single Universal Logical Fault Model. PRDC 2017: 217-218 - [c25]Masayoshi Yoshimura, Tomohiro Bouyashiki, Toshinori Hosokawa:
A Hardware Trojan Circuit Detection Method Using Activation Sequence Generations. PRDC 2017: 221-222 - 2016
- [c24]Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara:
A scheduling method for hierarchical testability based on test environment generation results. ETS 2016: 1-2 - 2015
- [c23]Masayoshi Yoshimura, Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa:
A Don't Care Filling Method to Reduce Capture Power Based on Correlation of FF Transitions. ATS 2015: 13-18 - [c22]Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara:
A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller Augmentation. ATS 2015: 37-42 - [c21]Atsushi Hirai, Yukari Yamauchi, Toshinori Hosokawa, Masayuki Arai:
A low capture power test generation method using capture safe test vectors. ETS 2015: 1-2 - 2013
- [j4]Hiroshi Yamazaki, Motohiro Wakazono, Toshinori Hosokawa, Masayoshi Yoshimura:
A Test Compaction Oriented Don't Care Identification Method Based on X-bit Distribution. IEICE Trans. Inf. Syst. 96-D(9): 1994-2002 (2013) - [c20]Hiroshi Yamazaki, Motohiro Wakazono, Toshinori Hosokawa, Masayoshi Yoshimura:
A don't care identification method for test compaction. DDECS 2013: 215-218 - [c19]Masayoshi Yoshimura, Amy Ogita, Toshinori Hosokawa:
A smart Trojan circuit and smart attack method in AES encryption circuits. DFTS 2013: 278-283 - 2010
- [j3]Ryoichi Inoue, Toshinori Hosokawa, Hideo Fujiwara:
A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint. IEICE Trans. Inf. Syst. 93-D(1): 24-32 (2010) - [c18]Masayoshi Yoshimura, Hiroshi Ogawa, Toshinori Hosokawa, Koji Yamazaki:
Evaluation of transition untestable faults using a multi-cycle capture test generation method. DDECS 2010: 273-276
2000 – 2009
- 2008
- [c17]Ryoichi Inoue, Toshinori Hosokawa, Hideo Fujiwara:
A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint. ATS 2008: 27-34 - 2007
- [c16]Toshinori Hosokawa, Ryoichi Inoue, Hideo Fujiwara:
Fault-dependent/independent Test Generation Methods for State Observable FSMs. ATS 2007: 275-280 - 2005
- [c15]Hideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara:
An Effective Design for Hierarchical Test Generation Based on Strong Testability. Asian Test Symposium 2005: 288-293 - 2004
- [j2]Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara:
A DFT Selection Method for Reducing Test Application Time of System-on-Chips. IEICE Trans. Inf. Syst. 87-D(3): 609-619 (2004) - 2003
- [c14]Michiaki Muraoka, Hideyuki Hamada, Hiroaki Nishi, Toshihiko Tada, Yoichi Onishi, Toshinori Hosokawa, Kenji Yoshida:
VCore-based design methodology. ASP-DAC 2003: 441-445 - [c13]Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara:
A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint. Asian Test Symposium 2003: 130-135 - [c12]Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara:
A DFT Selection Method for Reducing Test Application Time of System-on-Chips. Asian Test Symposium 2003: 412-417 - 2002
- [j1]Toshinori Hosokawa, Tomoo Inoue, Toshihiro Hiraoka, Hideo Fujiwara:
Test sequence compaction methods for acyclic sequential circuits using a time expansion model. Syst. Comput. Jpn. 33(10): 105-115 (2002) - [c11]Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka:
A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique. Asian Test Symposium 2002: 55-60 - [c10]Masayoshi Yoshimura, Toshinori Hosokawa, Mitsuyasu Ohta:
A Test Point Insertion Method to Reduce the Number of Test Patterns. Asian Test Symposium 2002: 298-304 - [c9]Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka:
A SoC Test Strategy Based on a Non-Scan DFT Method. Asian Test Symposium 2002: 305-310 - [c8]Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka:
A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits. VTS 2002: 328-335 - 2001
- [c7]Toshinori Hosokawa, Masayoshi Yoshimura, Mitsuyasu Ohta:
Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times. ASP-DAC 2001: 485-491
1990 – 1999
- 1999
- [c6]Toshinori Hosokawa, Toshihiro Hiraoka, Tomoo Inoue, Hideo Fujiwara:
Static and Dynamic Test Sequence Compaction Methods for Acyclic Sequential Circuits Using a Time Expansion Model. Asian Test Symposium 1999: 192- - 1998
- [c5]Tomoo Inoue, Toshinori Hosokawa, Takahiro Mihara, Hideo Fujiwara:
An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits. Asian Test Symposium 1998: 190-197 - 1997
- [c4]Toshinori Hosokawa, Toshihiro Hiraoka, Mitsuyasu Ohta, Michiaki Muraoka, Shigeo Kuninobu:
A Partial Scan Design Method Based on n-Fold Line-up Structures. Asian Test Symposium 1997: 306- - 1996
- [c3]Toshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka:
A Design for testability Method Using RTL Partitioning. Asian Test Symposium 1996: 88-93 - 1995
- [c2]Akira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka:
Design for testability using register-transfer level partial scan selection. ASP-DAC 1995 - 1993
- [c1]Akira Motohara, Toshinori Hosokawa, Michiaki Muraoka, Hidetsugu Maekawa, Kazuhiro Kayashima, Yasuharu Shimeki, Seichi Shin:
A State Traversal Algorithm Using a State Covariance Matrix. DAC 1993: 97-101
Coauthor Index
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