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ORCIDMiguel O. Arias-Estrada
Person information
- affiliation: National Institute of Astrophysics, Optics and Electronics (INAOE), Mexico
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2020 – today
- 2021
[j19]Berenice Rodríguez-Pedroza
, Miguel O. Arias-Estrada, José E. Mendoza-Torres:
A Variable Sampling-Time Method for Elliptical Orbit Motion Prediction in Nanosatellites. IEEE Access 9: 95767-95774 (2021)- [j18]Héctor-Daniel Vázquez-Delgado, Madaín Pérez Patricio, Abiel Aguilar-González, Miguel Octavio Arias-Estrada, Marco-Antonio Palacios-Ramos, Jorge-Luis Camas-Anzueto, Antonio Pérez Cruz, Sabino Velázquez-Trujillo:
Real-time multi-window stereo matching algorithm with fuzzy logic. IET Comput. Vis. 15(3): 208-223 (2021)
2010 – 2019
- 2019
- [j17]Abiel Aguilar-González, Miguel Arias-Estrada, Madaín Pérez Patricio, Jorge-Luis Camas-Anzueto:
An FPGA 2D-convolution unit based on the CAPH language. J. Real Time Image Process. 16(2): 305-319 (2019) - [j16]Abiel Aguilar-González, Miguel Arias-Estrada, François Berry, J. A. de Jesús Osuna-Coutiño:
The fastest visual ego-motion algorithm in the west. Microprocess. Microsystems 67: 103-116 (2019) - [j15]Abiel Aguilar-González, Miguel Arias-Estrada, François Berry:
Depth from a Motion Algorithm and a Hardware Architecture for Smart Cameras. Sensors 19(1): 53 (2019) - [c49]Walther Carballo-Hernández, François Berry, Maxime Pelcat, Miguel Arias-Estrada:
Towards Embedded Heterogeneous FPGA-GPU Smart Camera Architectures for CNN Inference. ICDSC 2019: 34:1-34:2 - 2018
- [j14]Abiel Aguilar-González, Miguel Arias-Estrada, François Berry:
Robust feature extraction algorithm suitable for real-time embedded applications. J. Real Time Image Process. 14(3): 647-665 (2018) - 2017
- [j13]Leonardo Chang, Airel Pérez Suárez, José Hernández Palancar, Miguel Arias-Estrada, Luis Enrique Sucar:
Improving visual vocabularies: a more discriminative, representative and compact bag of visual words. Informatica (Slovenia) 41(3) (2017) - [c48]Abiel Aguilar-González, Miguel Arias-Estrada, François Berry:
Dense Feature Matching Core for FPGA-based Smart Cameras. ICDSC 2017: 41-48 - [c47]Abiel Aguilar-González, Miguel Arias-Estrada, François Berry:
Camera Pose Estimation Suitable for Smart Cameras. ICDSC 2017: 202-204 - [c46]Walther Carballo-Hernández, Miguel Arias-Estrada:
Deep Learning Pulsed-based Convolutional Neuroprocessor Architecture on FPGAs. ICDSC 2017: 205-207 - [c45]J. A. de Jesús Osuna-Coutiño, Abiel Aguilar-González, Miguel Arias-Estrada:
GPU-based Visual Odometry for Autonomous Vehicle Applications. ICDSC 2017: 210-211 - [e1]Miguel O. Arias-Estrada, Christian Micheloni, Hamid K. Aghajan, Octavia I. Camps, Víctor M. Brea:
Proceedings of the 11th International Conference on Distributed Smart Cameras, Stanford, CA, USA, September 5-7, 2017. ACM 2017, ISBN 978-1-4503-5487-5 [contents] - 2016
- [j12]Madaín Pérez Patricio, Abiel Aguilar-González, Miguel O. Arias-Estrada, Héctor-Ricardo Hernandez-de Leon, Jorge-Luis Camas-Anzueto, J. A. de Jesús Osuna-Coutiño:
An FPGA stereo matching unit based on fuzzy logic. Microprocess. Microsystems 42: 87-99 (2016) - [c44]Abiel Aguilar-González, Miguel O. Arias-Estrada:
An FPGA Stereo Matching Processor Based on the Sum of Hamming Distances. ARC 2016: 66-77 - [c43]Abiel Aguilar-González, Miguel O. Arias-Estrada:
Towards a smart camera for monocular SLAM. ICDSC 2016: 128-135 - [c42]J. A. de Jesús Osuna-Coutiño, José Martínez-Carranza, Miguel O. Arias-Estrada, Walterio W. Mayol-Cuevas:
Dominant plane recognition in interior scenes from a single image. ICPR 2016: 1923-1928 - [c41]Abiel Aguilar-González, Miguel O. Arias-Estrada:
Dense mapping for monocular-SLAM. IPIN 2016: 1-8 - [c40]Claudia Cruz Martinez, José Martínez-Carranza, Walterio W. Mayol-Cuevas, Miguel O. Arias-Estrada:
Enhancing 3D Mapping via Real-Time Superpixel-based Segmentation. ISMAR Adjunct 2016: 90-95 - [c39]J. A. de Jesús Osuna-Coutiño, Claudia Cruz Martinez, José Martínez-Carranza, Miguel O. Arias-Estrada, Walterio W. Mayol-Cuevas:
I Want to Change My Floor: Dominant Plane Recognition from a Single Image to Augment the Scene. ISMAR Adjunct 2016: 135-140 - 2015
- [j11]Jorge D. Mendiola-Santibañez, Miguel O. Arias-Estrada, Israel Marcos Santillán-Méndez, Juvenal Rodríguez-Reséndiz, Martín Gallegos-Duarte, Domingo José Gomez-Melendez, Iván R. Terol-Villalobos:
Morphological Filtering Algorithm for Restoring Images Contaminated by Impulse Noise. Computación y Sistemas 19(2) (2015) - [j10]Eustolia Carreón, José Federico Ramírez-Cruz, Miguel O. Arias-Estrada, Edmundo Bonilla Huerta, Roberto Morales-Caporal:
Algoritmo evolutivo paralelo para aplicaciones en tomografía sísmica. Res. Comput. Sci. 94: 123-136 (2015) - [c38]Leonardo Chang, Airel Pérez Suárez, Máximo Rodríguez-Collada, José Hernández Palancar, Miguel O. Arias-Estrada, Luis Enrique Sucar:
Assessing the Distinctiveness and Representativeness of Visual Vocabularies. CIARP 2015: 331-338 - [c37]Abiel Aguilar-González, Madaín Pérez Patricio, Miguel O. Arias-Estrada, Jorge-Luis Camas-Anzueto, Héctor-Ricardo Hernandez-de Leon, Avisai Sanchez-Alegria:
An FPGA Correlation-Edge Distance approach for disparity map. CONIELECOMP 2015: 21-28 - 2014
- [j9]Jorge Domingo Mendiola-Santibañez, Martín Gallegos-Duarte, Miguel Octavio Arias-Estrada, Israel Marcos Santillán-Méndez, Juvenal Rodríguez-Reséndiz, Iván Ramón Terol-Villalobos:
Sequential application of viscous opening and lower leveling for three-dimensional brain extraction on magnetic resonance imaging T1. J. Electronic Imaging 23(3): 033010 (2014) - [c36]Leonardo Chang, Miguel O. Arias-Estrada, José Hernández Palancar, Luis Enrique Sucar:
Partial Shape Matching and Retrieval under Occlusion and Noise. CIARP 2014: 151-158 - [c35]Leonardo Chang, Miguel O. Arias-Estrada, José Hernández Palancar, Luis Enrique Sucar:
An Efficient Shape Feature Extraction, Description and Matching Method Using GPU. ICPRAM (Selected Papers) 2014: 206-221 - [c34]Leonardo Chang, Miguel O. Arias-Estrada, Luis Enrique Sucar, José Hernández Palancar:
LISF: An Invariant Local Shape Features Descriptor Robust to Occlusion. ICPRAM 2014: 429-437 - 2013
- [j8]Leonardo Chang, José Hernández Palancar, Luis Enrique Sucar, Miguel O. Arias-Estrada:
FPGA-based detection of SIFT interest keypoints. Mach. Vis. Appl. 24(2): 371-392 (2013) - 2012
- [c33]Maria Luisa Rosas-Cholula, Miguel O. Arias-Estrada:
Acceleration of the reflectance field acquisition using independent component analysis. CONIELECOMP 2012: 74-79 - [c32]Mario Alberto Mendoza-Barcenas, Eduardo Vizcaino Torres, Esaú Vicente Vivas, Miguel Arias-Estrada, Ignacio Mendoza Nucamendi, Jose Angel Colin Robles:
Embedded attitude control system for the educative satellite SATEDU. CONIELECOMP 2012: 118-123 - [c31]Modesto G. Medina-Meléndrez, Miguel O. Arias-Estrada, Albertina Castro:
Using a Scaling Factor in O(1/N) for the fixed-point implementation of the second-order goertzel filter. ISCAS 2012: 3218-3221 - [c30]Marco Aurelio Nuño-Maganda, Miguel O. Arias-Estrada, César Torres-Huitzil, Héctor Hugo Avilés-Arriaga, Yahir Hernandez-Mier, Miguel Morales-Sandoval:
A Hardware Architecture for Image Clustering Using Spiking Neural Networks. ISVLSI 2012: 261-266 - [i1]Maria-Luisa Sosas, Miguel-Octavio Arias:
Integrated three-dimensional reconstruction using reflectance fields. CoRR abs/1203.3114 (2012)
2000 – 2009
- 2009
- [j7]Jose Hugo Barron-Zambrano, Fernando Martin del Campo-Ramirez, Miguel O. Arias-Estrada:
Parallel Processor for 3D Recovery from Optical Flow. Int. J. Reconfigurable Comput. 2009: 973475:1-973475:11 (2009) - [j6]Modesto G. Medina-Meléndrez, Miguel O. Arias-Estrada, Albertina Castro:
Input and/or output pruning of composite length FFTs using a DIF-DIT transform decomposition. IEEE Trans. Signal Process. 57(10): 4124-4128 (2009) - [c29]Juan Carlos Moctezuma Eugenio, Miguel Arias-Estrada:
Hardware/Software FPGA Architecture for Robotics Applications. ARC 2009: 27-38 - [c28]Marco Aurelio Nuño-Maganda, Miguel O. Arias-Estrada, César Torres-Huitzil, Bernard Girau:
Hardware implementation of Spiking Neural Network classifiers based on backpropagation-based learning algorithms. IJCNN 2009: 2294-2301 - 2008
- [c27]M. Alejandra Menéndez O., D. Sosa G., Miguel O. Arias-Estrada, A. Espinosa M., J. E. Lara R.:
Creation of a 3D Robot Model and its Integration to a Microsoft Robotics Studio Simulation. SCSS (2) 2008: 143-146 - [c26]Griselda Saldaña, Miguel Arias-Estrada:
A Low-Level Image Processing Algorithms Accelerator Platform. CONIELECOMP 2008: 117-122 - [c25]César Torres-Huitzil, Bernard Girau, Miguel O. Arias-Estrada:
Biologically-Inspired Digital Architecture for a Cortical Model of Orientation Selectivity. ICANN (2) 2008: 188-197 - [c24]Rafael Lemuz-López, Miguel Arias-Estrada:
Ranking Corner Points by the Angular Difference between Dominant Edges. ICVS 2008: 323-332 - [c23]Jose Hugo Barron-Zambrano, Fernando Martin del Campo-Ramirez, Miguel O. Arias-Estrada:
Parallel Processor for 3D Recovery from Optical Flow. ReConFig 2008: 49-54 - 2007
- [j5]Griselda Saldaña, Miguel Arias-Estrada:
Compact FPGA-based systolic array architecture suitable for vision systems. Int. J. High Perform. Syst. Archit. 1(2): 124-132 (2007) - [c22]Marco Aurelio Nuño-Maganda, Miguel O. Arias-Estrada, César Torres-Huitzil:
High Performance Hardware Implementation of SpikeProp Learning: Potential and Tradeoffs. FPT 2007: 129-136 - [c21]Griselda Saldaña, Miguel Arias-Estrada:
Compact FPGA-based systolic array architecture suitable for vision systems. ITNG 2007: 1008-1013 - 2006
- [c20]Alicia Morales-Reyes, Miguel O. Arias-Estrada:
Stereo Analysis Extension Based on BRDF Reciprocity. CONIELECOMP 2006: 53 - [c19]Griselda Saldaña, Miguel Arias-Estrada:
Customizable FPGA-based architecture for video applications in real time. FPT 2006: 381-384 - [c18]Rafael Lemuz-López, Miguel Arias-Estrada:
Iterative Closest SIFT Formulation for Robust Feature Matching. ISVC (2) 2006: 502-513 - [c17]Rafael Lemuz-López, Miguel Arias-Estrada:
A Domain Reduction Algorithm for Incremental Projective Reconstruction. ISVC (2) 2006: 564-575 - [c16]Griselda Saldaña, Miguel Arias-Estrada:
Real Time FPGA-based Architecture for Video Applications. ReConFig 2006: 217-226 - 2005
- [j4]César Torres-Huitzil, Miguel O. Arias-Estrada:
FPGA-Based Configurable Systolic Architecture for Window-Based Image Processing. EURASIP J. Adv. Signal Process. 2005(7): 1024-1034 (2005) - [c15]Gerardo Sosa-Ramirez, Miguel Arias-Estrada:
3D Recovery with Free Hand Camera Motion. ENC 2005: 145-151 - [c14]Liz Castillo-Jimenez, Miguel Arias-Estrada:
Super-resolution with integrated radial distortion correction. ENC 2005: 165-173 - [c13]Marco Aurelio Nuño-Maganda, Miguel O. Arias-Estrada:
Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling. ReConFig 2005 - [c12]Griselda Saldaña, Miguel Arias-Estrada:
FPGA-based customizable systolic architecture for image processing applications. ReConFig 2005 - 2004
- [j3]César Torres-Huitzil, Miguel O. Arias-Estrada:
Real-time image processing with a compact FPGA-based systolic architecture. Real Time Imaging 10(3): 177-187 (2004) - 2003
- [c11]César Torres-Huitzil, Miguel O. Arias-Estrada:
Configurable Hardware Architecture for Real-Time Window-Based Image Processing. FPL 2003: 1008-1011 - [c10]Juan M. Xicoténcatl Pérez, Miguel Arias-Estrada:
FPGA Based High Density Spiking Neural Network Array. FPL 2003: 1053-1056 - [c9]Selene Maya-Rueda, Miguel O. Arias-Estrada:
FPGA Processor for Real-Time Optical Flow Computation. FPL 2003: 1103-1106 - [c8]Marco Aurelio Nuño-Maganda, Miguel O. Arias-Estrada, Claudia Feregrino Uribe:
Three video applications using an FPGA based pyramid implementation: Tracking, Mosaics and Stabilization. FPT 2003: 336-339 - 2002
- [c7]Miguel Arias-Estrada, Eduardo Rodríguez-Palacios:
An FPGA Co-processor for Real-Time Visual Tracking. FPL 2002: 710-719 - [c6]César Torres-Huitzil, Selene Maya-Rueda, Miguel O. Arias-Estrada:
A reconfigurable vision system for real-time applications. FPT 2002: 286-289 - 2001
- [j2]Miguel O. Arias-Estrada, César Torres-Huitzil:
Real-time field programmable gate array architecture for computer vision. J. Electronic Imaging 10(1): 289-296 (2001) - [c5]Miguel Arias-Estrada, Juan M. Xicoténcatl Pérez:
Multiple Stereo Matching Using an Extended Architecture. FPL 2001: 203-212 - 2000
- [c4]César Torres-Huitzil, Miguel O. Arias-Estrada:
An FPGA Architecture for High Speed Edge and Corner Detection. CAMP 2000: 112-116 - [c3]Selene Maya, M. Rocio Reynoso, César Torres-Huitzil, Miguel O. Arias-Estrada:
Compact Spiking Neural Network Implementation in FPGA. FPL 2000: 270-276 - [c2]Juan Jaime Vega, M. Rocio Reynoso, Miguel Arias-Estrada, Leopoldo Altamirano Robles:
Bragg Curve Identification Using a Neural Network. IJCNN (4) 2000: 379-382
1990 – 1999
- 1999
- [c1]A. Lecerf, François Vachon, D. Ouellet, Miguel O. Arias-Estrada:
FPGA Based Computer Vision Camera. FPGA 1999: 248 - 1996
- [j1]Miguel O. Arias-Estrada, Marc Tremblay, Denis Poussart:
A Focal Plane Architecture for Motion Computation. Real Time Imaging 2(6): 351-360 (1996)
Coauthor Index
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