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Walter Brown
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2010 – 2019
- 2016
- [j1]Cunxi Yu
, Walter Brown, Duo Liu, André Rossi
, Maciej J. Ciesielski:
Formal Verification of Arithmetic Circuits by Function Extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2131-2142 (2016) - 2015
- [c8]Maciej J. Ciesielski, Cunxi Yu, Walter Brown, Duo Liu, André Rossi
:
Verification of gate-level arithmetic circuits by function extraction. DAC 2015: 52:1-52:6 - [c7]Cunxi Yu, Walter Brown, Maciej J. Ciesielski:
Verification of arithmetic datapath designs using word-level approach - A case study. ISCAS 2015: 1862-1865 - [c6]Samaneh Ghandali, Cunxi Yu, Duo Liu, Walter Brown, Maciej J. Ciesielski:
Logic Debugging of Arithmetic Circuits. ISVLSI 2015: 113-118 - 2014
- [c5]Maciej J. Ciesielski, Walter Brown, Duo Liu, André Rossi
:
Function Extraction from Arithmetic Bit-Level Circuits. ISVLSI 2014: 356-361 - 2013
- [c4]Maciej J. Ciesielski, Walter Brown, André Rossi:
Arithmetic Bit-Level Verification Using Network Flow Model. Haifa Verification Conference 2013: 327-343
2000 – 2009
- 2009
- [c3]Walter Brown, Irwin Brown:
Towards a research framework for a human development-based "bottom of the pyramid" ICT development strategy in South Africa. ECIS 2009: 1223-1234 - [c2]Walter Brown:
Innovations for digital inclusion: Leveraging next generation networks for human development from the bottom of the pyramid. Kaleidoscope 2009: 1-8 - 2008
- [c1]Walter Brown, Irwin Brown
:
Next generation ICT policy in South Africa: Towards a human development-based ICT policy. HCC 2008: 109-123
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