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ORCIDSujit Kumar Patel
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2020 – today
- 2024
[j16]Konudula Anjali Rao
, Abhishek Kumar, Sujit Kumar Patel, Dmitry I. Kaplun, Neetesh Purohit:
Design of Frequency Sampling Rational Rate Polyphase FIR Converter. IEEE Trans. Circuits Syst. II Express Briefs 71(2): 962-966 (2024)- 2023
- [j15]Konudula Anjali Rao, Abhishek Kumar, Dmitrii I. Kaplun, Sujit Kumar Patel, Neetesh Purohit:
Design of low complexity parallel polyphase finite impulse response filter using coefficient symmetry. IET Circuits Devices Syst. 17(1): 29-37 (2023) - [j14]Anuradha, Sujit Kumar Patel, Subodh Kumar Singhal:
An area-delay efficient single-precision floating-point multiplier for VLSI systems. Microprocess. Microsystems 98: 104798 (2023) - 2021
- [j13]Shireesh Kumar Rai, Rishikesh Pandey, Bharat Garg, Sujit Kumar Patel:
A novel design of current differencing transconductance amplifier with high transconductance gain and enhanced bandwidth. Turkish J. Electr. Eng. Comput. Sci. 29(1): 454-469 (2021) - [j12]Subodh Kumar Singhal, Sujit Kumar Patel, Anurag Mahajan, Gaurav Saxena:
Area-delay efficient Radix-4 8×8 Booth multiplier for DSP applications. Turkish J. Electr. Eng. Comput. Sci. 29(4): 2012-2028 (2021) - [j11]Bharat Garg, Sujit Kumar Patel:
Reconfigurable Carry Look-Ahead Adder Trading Accuracy for Energy Efficiency. J. Signal Process. Syst. 93(1): 99-111 (2021) - [j10]Bharat Garg, Sujit Kumar Patel:
Reconfigurable Rounding Based Approximate Multiplier for Energy Efficient Multimedia Applications. Wirel. Pers. Commun. 118(2): 919-931 (2021) - 2020
- [j9]Sujit Kumar Patel, Bharat Garg, Shireesh Kumar Rai:
A power and area efficient approximate carry skip adder for error resilient applications. Turkish J. Electr. Eng. Comput. Sci. 28(1): 443-457 (2020) - [j8]Sujit Kumar Patel, Bharat Garg, Shireesh Kumar Rai:
An Efficient Accuracy Reconfigurable CLA Adder Designs Using Complementary Logic. J. Electron. Test. 36(1): 135-142 (2020) - [j7]Bharat Garg, Sujit Kumar Patel, Sunil Dutt:
LoBA: A Leading One Bit Based Imprecise Multiplier for Efficient Image Processing. J. Electron. Test. 36(3): 429-437 (2020) - [j6]Sujit Kumar Patel, Subodh Kumar Singhal:
Area-delay and energy efficient multi-operand binary tree adder. IET Circuits Devices Syst. 14(5): 586-593 (2020) - [j5]Subodh Kumar Singhal, Basant K. Mohanty, Sujit Kumar Patel, Gaurav Saxena:
Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder. J. Circuits Syst. Comput. 29(12): 2050186:1-2050186:20 (2020)
2010 – 2019
- 2019
- [c1]Sujit Kumar Patel, Bharat Garg, Anurag Mahajan, Shireesh Kumar Rai:
Area-Delay Efficient and Low-Power Carry Skip Adder for High Performance Computing Systems. iSES 2019: 300-303 - 2016
- [j4]Basant K. Mohanty, Pramod Kumar Meher, Sujit Kumar Patel:
LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1926-1935 (2016) - 2015
- [j3]Basant Kumar Mohanty, Sujit Kumar Patel:
Efficient very large-scale integration architecture for variable length block least mean square adaptive filter. IET Signal Process. 9(8): 605-610 (2015) - [j2]Pramod Kumar Meher, Basant Kumar Mohanty, Sujit Kumar Patel, Soumya Ganguly, Thambipillai Srikanthan:
Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(12): 2836-2845 (2015) - 2014
- [j1]Basant Kumar Mohanty, Sujit Kumar Patel:
Area-Delay-Power Efficient Carry-Select Adder. IEEE Trans. Circuits Syst. II Express Briefs 61-II(6): 418-422 (2014)
Coauthor Index
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