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2010 – 2019
- 2018
[j3]Yeunhee Huh, Sung-Wan Hong
, Sang-Hui Park, Changsik Shin, Jun-Suk Bang, Changbyung Park, Sungsoo Park, Gyu-Hyeong Cho:
A 10.1" 183-µW/electrode, 0.73-mm2/sensor High-SNR 3-D Hover Sensor Based on Enhanced Signal Refining and Fine Error Calibrating Techniques. IEEE J. Solid State Circuits 53(4): 1079-1088 (2018)- [c4]Se-Un Shin, Yeunhee Huh, Yong-Min Ju, Sung-Won Choi, Changsik Shin, Young-Jin Woo, Minseong Choi, Se-Hong Park, Young-Hoon Sohn, Min-Woo Ko, Youngsin Jo, Hyun-Ki Han, Hyung-Min Lee, Sung-Wan Hong, Wanyuan Qu, Gyu-Hyeong Cho:
A 95.2% efficiency dual-path DC-DC step-up converter with continuous output current delivery and low voltage ripple. ISSCC 2018: 430-432 - 2016
- [c3]Se-un Shin, Min-Yong Jung, Kiduk Kim, Sang-Hui Park, Yeunhee Huh, Changsik Shin, Se-Hong Park, Jun-Suk Bang, Jong-Beom Baek, Sung-Won Choi, Yong-Min Ju, Gyu-Hyeong Cho:
A reconfigurable SIMO system with 10-output dual-bus DC-DC converter using the load balancing function in group allocator for diversified load condition. VLSI Circuits 2016: 1-2 - 2015
- [c2]Sang-Han Lee, Jun-Suk Bang, Kye-Seok Yoon, Sung-Wan Hong, Changsik Shin, Min-Yong Jung, Gyu-Hyeong Cho:
12.1 A 0.518mm2 quasi-current-mode hysteretic buck DC-DC converter with 3μs load transient response in 0.35μm BCDMOS. ISSCC 2015: 1-3 - 2011
- [j2]Lee-eun Yu, Changsik Shin, Seungwhun Paik, Jing-Jia Liou, Youngsoo Shin:
Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits with Clock Networks. J. Circuits Syst. Comput. 20(8): 1547-1569 (2011)
2000 – 2009
- 2009
- [j1]Eunjoo Choi, Changsik Shin, Youngsoo Shin:
ssr HLShbox-ssr pg: High-Level Synthesis of Power-Gated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 451-456 (2009) - 2008
- [c1]Eunjoo Choi, Changsik Shin, Taewhan Kim, Youngsoo Shin:
Power-gating-aware high-level synthesis. ISLPED 2008: 39-44
Coauthor Index
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