default search action
Ching-Che Chung
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2024
- [j35]Yu-Pei Liang, Chen-Ming Chang, Ching-Che Chung:
Implementation of Lightweight Convolutional Neural Networks with an Early Exit Mechanism Utilizing 40 nm CMOS Process for Fire Detection in Unmanned Aerial Vehicles. Sensors 24(7): 2265 (2024) - [j34]Yu-Pei Liang, Yao-Shun Hsu, Ching-Che Chung:
A Low-Power Hierarchical CNN Hardware Accelerator for Bearing Fault Diagnosis. IEEE Trans. Instrum. Meas. 73: 1-11 (2024) - 2023
- [j33]Ching-Che Chung, Yu-Pei Liang, Hong-Jin Jiang:
CNN Hardware Accelerator for Real-Time Bearing Fault Diagnosis. Sensors 23(13): 5897 (2023) - [j32]Yu-Pei Liang, Ming-You Hung, Ching-Che Chung:
A Multiplier-Free Convolution Neural Network Hardware Accelerator for Real-Time Bearing Condition Detection of CNC Machinery. Sensors 23(23): 9437 (2023) - [c25]Ching-Che Chung, Yu-Pei Liang, Jo-Chen Huang:
Lightweight CNN hardware accelerator using the ternary quantization method for fault diagnosis of CNC machinery. ICCE-Taiwan 2023: 133-134 - 2022
- [j31]Tsung-Hsien Liu, Ting-Xu Jiang, Ching-Che Chung, Yuan-Sun Chu:
A Maximum Logarithmic Maximum a Posteriori Probability Based Soft-Input Soft-Output Detector for the Coded Spatial Modulation Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 69(9): 3816-3828 (2022) - [c24]Ching-Che Chung, Yi-Ting Tsai:
A Body Channel Communication Transceiver with a 16x Oversampling CDR and Convolutional Codes. VLSI-DAT 2022: 1-4 - 2020
- [j30]Ching-Che Chung, Duo Sheng, Ming-Hsuan Li:
Design of a human body channel communication transceiver using convolutional codes. Microelectron. J. 100: 104783 (2020) - [c23]Ching-Che Chung, Huai-Xiang Zhang, Ming-You Hung, Hong-Jin Jian:
A DBN Hardware Accelerator for Auditory Scene Classification. ICCE-TW 2020: 1-2
2010 – 2019
- 2019
- [j29]Ching-Che Chung, Duo Sheng, Ming-Chieh Li, Yi-Che Tsai:
A fast phase tracking reference-less all-digital CDR circuit for human body channel communication. Microelectron. J. 84: 87-95 (2019) - [c22]Ching-Che Chung, Wei-Jung Chu, Yi-Ting Tsai:
Built-in Self-Test Circuits for All-digital Phase-Locked Loops. ICCE-TW 2019: 1-2 - [c21]Ching-Che Chung, Yi-Zeng Lee, Huai-Xiang Zhang:
Design of a DBN Hardware Accelerator for Handwritten Digit Recognitions. ICCE-TW 2019: 1-2 - [c20]Ching-Che Chung, Hsin-Han Huang:
An All-Digital Temperature Sensor with Process and Voltage Variation Tolerance for IoT Applications. SoCC 2019: 109-112 - 2017
- [j28]Ching-Che Chung, Jhih-Wei Li:
A cell-based 5-MHz on-chip clock generator. Turkish J. Electr. Eng. Comput. Sci. 25: 1472-1482 (2017) - [j27]Ching-Che Chung, Chien-Ying Yu:
An area-efficient and wide-range digital DLL for per-pin deskew applications. Turkish J. Electr. Eng. Comput. Sci. 25: 2185-2194 (2017) - [j26]Ching-Che Chung, Chi-Yu Hou:
An all-digital delay-locked loop for 3-D ICs die-to-die clock deskew applications. Microelectron. J. 70: 63-71 (2017) - [c19]Ching-Che Chung, Yi-Che Tsai, Ming-Chieh Li:
A reference-less all-digital transceiver for human body channel communication. VLSI-DAT 2017: 1-4 - 2016
- [j25]Ching-Che Chung, Chi-Kuang Lo:
A fast lock-in all-digital phase-locked loop in 40-nm CMOS technology. IEICE Electron. Express 13(17): 20160749 (2016) - [j24]Ching-Che Chung, Wei-Siang Su, Chi-Kuang Lo:
A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 408-412 (2016) - [c18]Ching-Che Chung, Mei-I Sun:
An all-digital voltage sensor for static voltage drop measurements. SAS 2016: 1-4 - 2015
- [j23]Ching-Che Chung, Duo Sheng, Wei-Da Ho:
A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator. IEEE Trans. Very Large Scale Integr. Syst. 23(5): 983-987 (2015) - [j22]Ching-Che Chung, Duo Sheng, Chang-Jun Li:
A Wide-Range Low-Cost All-Digital Duty-Cycle Corrector. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2487-2496 (2015) - [c17]Ching-Che Chung, Chi-Tung Chang, Chih-Yu Lin:
A 1 Mb/s-40 Mb/s human body channel communication transceiver. VLSI-DAT 2015: 1-4 - 2014
- [j21]Duo Sheng, Ching-Che Chung, Hsiu-Fan Lai, Shu-Syun Jhao:
High-resolution and all-digital on-chip delay measurement with low supply sensitivity for SoC applications. IEICE Electron. Express 11(3): 20131011 (2014) - [j20]Ching-Che Chung, Duo Sheng, Sung-En Shen:
High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 1096-1105 (2014) - [j19]Ching-Che Chung, Hao-Hsiang Hsu:
Partial Parity Cache and Data Cache Management Method to Improve the Performance of an SSD-Based RAID. IEEE Trans. Very Large Scale Integr. Syst. 22(7): 1470-1480 (2014) - [c16]Ching-Che Chung, Jhih-Wei Li:
An all-digital on-chip abnormal temperature warning sensor for dynamic thermal management. SoCC 2014: 221-224 - [c15]Ching-Che Chung, Chi-Yu Hou:
All-digital delay-locked loop for 3D-IC die-to-die clock synchronization. VLSI-DAT 2014: 1-4 - [c14]Ching-Che Chung, Duo Sheng, Chen-Han Chen:
An all-digital phase-locked loop compiler with liberty timing files. VLSI-DAT 2014: 1-4 - 2013
- [j18]Ching-Che Chung, Duo Sheng, Wei-Da Ho:
A counter-based all-digital spread-spectrum clock generator with high EMI reduction in 65nm CMOS. IEICE Electron. Express 10(6): 20130090 (2013) - [c13]Duo Sheng, Ching-Che Chung, Chih-Chung Huang, Jia-Wei Jian:
A high-resolution and one-cycle conversion time-to-digital converter architecture for PET image applications. EMBC 2013: 2461-2464 - [c12]Ching-Che Chung, Jhih-Wei Li:
An all-digital on-chip silicon oscillator with automatic VT range selection relative modeling. ISCAS 2013: 2682-2685 - [c11]Ching-Che Chung, Chang-Jun Li:
A low-power delay-recycled all-digital duty-cycle corrector with unbalanced process variations tolerance. VLSI-DAT 2013: 1-4 - [c10]Ching-Che Chung, Duo Sheng, Wei-Siang Su:
A 0.5V/1.0V fast lock-in ADPLL for DVFS battery-powered devices. VLSI-DAT 2013: 1-4 - 2012
- [j17]Ching-Che Chung, Duo Sheng, Ning-Mi Hsueh:
A high-performance wear-leveling algorithm for flash memory system. IEICE Electron. Express 9(24): 1874-1880 (2012) - [j16]Ching-Che Chung, Duo Sheng, Chia-Lin Chang, Wei-Da Ho, Yang-Di Lin, Fang-Nien Lu:
An All-Digital Large-N Audio Frequency Synthesizer for HDMI Applications. IEEE Trans. Circuits Syst. II Express Briefs 59-II(7): 424-428 (2012) - [j15]Chien-Ying Yu, Ching-Che Chung, Chia-Jung Yu, Chen-Yi Lee:
A Low-Power DCO Using Interlaced Hysteresis Delay Cells. IEEE Trans. Circuits Syst. II Express Briefs 59-II(10): 673-677 (2012) - [c9]Ching-Che Chung, Ning-Mi Hsueh:
A low-complexity high-performance wear-leveling algorithm for flash memory system design. APCCAS 2012: 595-598 - [c8]Ching-Che Chung, Duo Sheng, Wei-Da Ho:
A low-power and small-area all-digital spread-spectrum clock generator in 65nm CMOS technology. VLSI-DAT 2012: 1-4 - 2011
- [j14]Ching-Che Chung, Duo Sheng, Chia-Lin Chang:
A 600kHz to 1.2GHz all-digital delay-locked loop in 65nm CMOS technology. IEICE Electron. Express 8(7): 518-524 (2011) - [j13]Ching-Che Chung, Duo Sheng, Sung-En Shen:
A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology. IEICE Electron. Express 8(15): 1245-1251 (2011) - [j12]Ching-Che Chung, Chiun-Yao Ko:
A Fast Phase Tracking ADPLL for Video Pixel Clock Generation in 65 nm CMOS Technology. IEEE J. Solid State Circuits 46(10): 2300-2311 (2011) - [j11]Ching-Che Chung, Cheng-Ruei Yang:
An Autocalibrated All-Digital Temperature Sensor for On-Chip Thermal Monitoring. IEEE Trans. Circuits Syst. II Express Briefs 58-II(2): 105-109 (2011) - [j10]Ching-Che Chung, Chiun-Yao Ko, Sung-En Shen:
Built-in Self-Calibration Circuit for Monotonic Digitally Controlled Oscillator Design in 65-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 58-II(3): 149-153 (2011) - [j9]Duo Sheng, Ching-Che Chung, Chen-Yi Lee:
A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 1113-1117 (2011) - [j8]Ching-Che Chung, Jui-Yuan Yu, Shiou-Ru Jang, Chen-Yi Lee:
A 90 nm All-digital Smart Temperature Sensor with Wireless Body Area Network Baseband Transceiver for Biotelemetry Applications. J. Signal Process. Syst. 64(2): 241-248 (2011) - 2010
- [j7]Duo Sheng, Ching-Che Chung, Chen-Yi Lee:
Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications. IEICE Electron. Express 7(9): 634-639 (2010) - [c7]Ching-Che Chung, Cheng-Ruei Yang:
An all-digital smart temperature sensor with auto-calibration in 65nm CMOS technology. ISCAS 2010: 4089-4092
2000 – 2009
- 2008
- [j6]Jui-Yuan Yu, Ching-Che Chung, Chen-Yi Lee:
A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems. IEEE Trans. Circuits Syst. II Express Briefs 55-II(9): 922-926 (2008) - [c6]Duo Sheng, Ching-Che Chung, Chen-Yi Lee:
An all digital spread spectrum clock generator with programmable spread ratio for SoC applications. APCCAS 2008: 850-853 - 2007
- [j5]Duo Sheng, Ching-Che Chung, Chen-Yi Lee:
An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications. IEEE Trans. Circuits Syst. II Express Briefs 54-II(11): 954-958 (2007) - [c5]Jui-Yuan Yu, Ching-Che Chung, Wan-Chun Liao, Chen-Yi Lee:
A sub-mW Multi-Tone CDMA Baseband Transceiver Chipset for Wireless Body Area Network Applications. ISSCC 2007: 364-609 - [c4]Jui-Yuan Yu, Juinn-Ting Chen, Mei-Hui Yang, Ching-Che Chung, Chen-Yi Lee:
An all-digital phase-frequency tunable clock generator for wireless OFDM communications systems. SoCC 2007: 305-308 - 2006
- [j4]Pao-Lung Chen, Ching-Che Chung, Jyh-Neng Yang, Chen-Yi Lee:
A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications. IEEE J. Solid State Circuits 41(6): 1275-1285 (2006) - [c3]Duo Sheng, Ching-Che Chung, Chen-Yi Lee:
A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications. APCCAS 2006: 105-108 - [c2]Tsu-Ming Liu, Ching-Che Chung, Chen-Yi Lee, Ting-An Lin, Sheng-Zen Wang:
Design of a 125muW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications. DAC 2006: 288-289 - 2005
- [j3]Pao-Lung Chen, Ching-Che Chung, Chen-Yi Lee:
A portable digitally controlled oscillator using novel varactors. IEEE Trans. Circuits Syst. II Express Briefs 52-II(5): 233-237 (2005) - [c1]Pao-Lung Chen, Ching-Che Chung, Chen-Yi Lee:
An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications. ISCAS (5) 2005: 4875-4878 - 2004
- [j2]Ching-Che Chung, Chen-Yi Lee:
A new DLL-based approach for all-digital multiphase clock generation. IEEE J. Solid State Circuits 39(3): 469-475 (2004) - 2003
- [j1]Ching-Che Chung, Chen-Yi Lee:
An all-digital phase-locked loop for high-speed clock generation. IEEE J. Solid State Circuits 38(2): 347-351 (2003)
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from , , and to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-05-19 00:13 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint