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Kairang Chen
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2020 – today
- 2020
- [c5]Yinan Wang
, Xiangyu Liu, Håkan Johansson, Chengxuan Zhao, Kairang Chen, Xi Zhu:
On First-Order Compensation of Timing Mismatch in Two-Channel TIADCs. ISCAS 2020: 1-5
2010 – 2019
- 2018
- [j1]Daiguo Xu
, Lei Qiu
, Zhengping Zhang, Tao Liu, Lu Liu, Kairang Chen, Shiliu Xu:
A Linearity-Improved 8-bit 320-MS/s SAR ADC With Metastability Immunity Technique. IEEE Trans. Very Large Scale Integr. Syst. 26(8): 1545-1553 (2018) - 2016
- [c4]Kairang Chen, Atila Alvandpour:
Capacitive charge pump gain-stage with source follower buffers for pipelined SAR ADCs. ISIC 2016: 1-4 - [c3]Kairang Chen, Atila Alvandpour:
Design of a gain-stage for pipelined SAR ADC using capacitive charge pump. MIXDES 2016: 187-190 - [c2]Kairang Chen, Martin Nielsen-Lönn
, Atila Alvandpour:
Asynchronous clock generator for a 14-bit two-stage pipelined SAR ADC in 0.18 μm CMOS. NORCAS 2016: 1-4 - 2015
- [c1]Kairang Chen, Quoc-Tai Duong, Atila Alvandpour:
Power analysis for two-stage high resolution pipeline SAR ADC. MIXDES 2015: 496-499
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