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2010 – 2019
- 2014
[c13]Jui-Sheng Lee, Hsiu-Cheng Chang, Jiun-In Guo:
An Adaboost-based two-level moving object detection architecture with dynamic ROI allocation. ICCE-TW 2014: 103-104- [c12]Kai-Chen Huang, Po-Yu Chien, Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo:
A 360-degree panoramic video system design. VLSI-DAT 2014: 1-4 - 2013
- [c11]Jui-Sheng Lee, Yuan-Hsiang Miao, Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo:
A view scalable multi-view video decoder system. VLSI-DAT 2013: 1-4 - 2012
- [j4]Cheng-An Chien, Guo-An Jian, Hsiu-Cheng Chang, Kuan-Hung Chen, Jiun-In Guo:
High efficiency data access system architecture for deblocking filter supporting multiple video coding standards. IEEE Trans. Consumer Electron. 58(2): 670-678 (2012) - [c10]Jui-Sheng Lee, Sheng-Han Wang, Chih-Tai Chou, Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo:
An inter-frame/inter-view cache architecture design for multi-view video decoders. APSIPA 2012: 1-4 - [c9]Cheng-Yen Chang, Cheng-An Chien, Hsiu-Cheng Chang, Jia-Wei Chen, Jiun-In Guo:
A two level mode decision algorithm for H.264 high profile intra encoding. ISCAS 2012: 508-511 - 2011
- [j3]Jia-Wei Chen, Hsiu-Cheng Chang, Jinn-Shyan Wang, Jiun-In Guo:
A dynamic quality-adjustable H.264 intra coder. IEEE Trans. Consumer Electron. 57(3): 1203-1211 (2011) - [c8]Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang, Ching-Hwa Cheng:
A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. ASP-DAC 2011: 73-74
2000 – 2009
- 2009
- [j2]Hsiu-Cheng Chang, Jia-Wei Chen, Bing-Tsung Wu, Ching-Lung Su, Jinn-Shyan Wang, Jiun-In Guo:
A Dynamic Quality-Adjustable H.264 Video Encoder for Power-Aware Video Applications. IEEE Trans. Circuits Syst. Video Technol. 19(12): 1739-1754 (2009) - [c7]Hsiu-Cheng Chang, Yao-Chang Yang, Jia-Wei Chen, Ching-Lung Su, Cheng-An Chien, Jiun-In Guo, Jinn-Shyan Wang:
A dynamic quality-scalable H.264 video encoder chip. ASP-DAC 2009: 125-126 - [c6]Hsiu-Cheng Chang, Jia-Wei Chen, Yao-Chang Yang, Cheng-An Chien, Tzu-Chun Chang, Jinn-Shyan Wang, Jiun-In Guo:
A Dynamic Quality-scalable H.264 Video Encoder. ISCAS 2009: 1932 - [c5]Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo:
A High Throughput Deblocking Filter Design Supporting Multiple Video Coding Standards. ISCAS 2009: 2377-2380 - 2008
- [c4]Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo:
A high throughput in-loop de-blocking filter supporting H.264/AVC BP/MP/HP video coding. APCCAS 2008: 312-315 - 2007
- [j1]Chien-Chang Lin, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Yi-Huan Ou-Yang
, Ming-Chih Tsai, Jiun-In Guo, Jinn-Shyan Wang:
A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications. IEEE J. Solid State Circuits 42(1): 170-182 (2007) - [c3]Hsiu-Cheng Chang, Jia-Wei Chen, Ching-Lung Su, Yao-Chang Yang, Yao Li, Chun-Hao Chang, Ze-Min Chen, Wei-Sen Yang, Chien-Chang Lin, Ching-Wen Chen, Jinn-Shyan Wang, Jiun-In Guo:
A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip. ISSCC 2007: 280-603 - [c2]Chun-Hao Chang, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Jinn-Shyan Wang, Jiun-In Guo:
A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons. SiPS 2007: 521-526 - 2005
- [c1]Hsiu-Cheng Chang, Chien-Chang Lin, Jiun-In Guo:
A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding. ISCAS (6) 2005: 6110-6113
Coauthor Index
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