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2020 – today
- 2023
[c52]Jian-Lin Zeng, Tsung-Yi Wu, Don-Gey Liu, Ching-Hwa Cheng:
Live Demonstration: A Low-Power Dual-Core Motion Estimation Chip Design and Validation for a Wireless Panoramic Endoscopy. ISCAS 2023: 1- [c51]Jian-Lin Zeng, Tsung-Yi Wu, Don-Gey Liu, Ching-Hwa Cheng:
A Low-Power Dual-Core Motion Estimation Chip Design and Validation for a Wireless Panoramic Endoscopy. ISCAS 2023: 1-5 - 2022
- [c50]Xiang-Ren Yang, Sheng-Wei Hsu, Ching-Hwa Cheng, Don-Gey Liu:
A Low Power Two Lenses Wireless Panoramic Micro-Endoscopy Implemented Using Voltage-Current Adjuster and 3D-PCB Stacking Technology. BioCAS 2022: 1-5 - [c49]Ching-Hwa Cheng, Don-Gey Liu:
Live Demonstration: A Portable Four-Lenses Panoramic-Stereo Endoscope System Development. BioCAS 2022: 243 - 2021
- [j10]Song-Toan Tran
, Ching-Hwa Cheng, Don-Gey Liu:
A Multiple Layer U-Net, Un-Net, for Liver and Liver Tumor Segmentation in CT. IEEE Access 9: 3752-3764 (2021) - [c48]Thanh-Tuan Nguyen, Ching-Hwa Cheng, Don-Gey Liu, Song-Toan Tran, Minh-Hai Le:
An Overlapping and Leading Edge Detection Combined Technique for Distance Estimation under High-Background Lights in a Pulsed-LiDAR System. IECC 2021: 11-16 - [c47]Ching-Hwa Cheng, Ching-Kun Chao, Kai-Chun Yeh, Don-Gey Liu, Sheng-Di Lin:
The Performance-Complexity Efficient Time-to-Digit and Data-Processing Chips Design and Validation for a LiDAR System. ISCAS 2021: 1-4 - [c46]Pham Minh Dung, Ching-Hwa Cheng, Don-Gey Liu:
An Intelligent Image-Based Force Sensing System Development to Assist Robot-Arm Surgery. ISCAS 2021: 1-5 - 2020
- [c45]Ching-Hwa Cheng:
A Real-Time Robot-Arm Surgical Guiding System Development by Image-Tracking. AICAS 2020: 133 - [c44]Ching-Hwa Cheng:
A Quantity Evaluation and Reconfiguration Mechanism for Signal- and Power-Interconnections in 3D-Stacking System. ASP-DAC 2020: 7-8 - [c43]Ching-Hwa Cheng, Pham Minh Dung, Tang-Chieh Liu:
Development of a Portable Self-Guidance Rescue Car and a 3D-Screen LIDAR Mapping System. ISCAS 2020: 1 - [c42]Ching-Hwa Cheng, Huy Anh Nguyen, Tang-Chieh Liu:
Design and Implementation of a Pre-Surgical Investigation System by VR+AR+MR Techniques. ISCAS 2020: 1 - [c41]Ching-Hwa Cheng, Jiun-In Guo:
Low-Power 3D-PCB Stacking System Design and Validation by Automatic Voltage-Current Scalable Technique. VLSI-DAT 2020: 1-2
2010 – 2019
- 2019
- [c40]I-Lok Cheng, Ching-Hwa Cheng, Don-Gey Liu:
A Learnable Unmanned Smart Logistics Prototype System Design and Implementation. AICAS 2019: 221-224 - [c39]Ching-Hwa Cheng, Tang-Chieh Liu:
Digitalized-Management Voltage-Domain Programmable Mechanisms for Dual-Vdd Low-Power Embedded Digital Systems. DDECS 2019: 1-4 - [c38]Dinh Thai Kim, Ching-Hwa Cheng, Don-Gey Liu:
A Stable Video Stitching Technique for Minimally Invasive Surgery. ICBET 2019: 266-269 - 2016
- [c37]An-Tai Xiao, Yung-Siang Miao, Ching-Hwa Cheng, Jiun-In Guo:
A variable-voltage low-power technique for digital circuit system. ASP-DAC 2016: 13-14 - [c36]Yu-Shin Wang, Ching-Hwa Cheng:
A hierarchy multiple-voltage design technique for low-power performance-manageable bio-chips. ICCE-TW 2016: 1-2 - 2015
- [j9]Ching-Hwa Cheng:
SCKVdd: A Scalable Clock-Controlled Self-Stabilized Voltage Technique for Low Power CMOS Digital Circuits. ACM J. Emerg. Technol. Comput. Syst. 12(1): 10:1-10:24 (2015) - [c35]Hsiu-Cheng Lee, Jen-Bo Wang, Kai-Hsiang Juang, Kuo-Ching Hsiao, Hsung-Bie Chang, Yeng-Ting Lu, Ching-Sung Lee, Ming-Hsueh Hsiau, Qi-Ming Wan, Vu Duc Thai, Ching-Hwa Cheng, Don-Gey Liu:
An ECG front-end circuit with single power supply. ICCE-TW 2015: 270-271 - [c34]Ching-Hwa Cheng, Sheng-Ping Hung, Jiun-In Guo, Kai-Che Liu, Jungle Chi-Hsiang Wu:
A wireless panoramic endoscope system design and implementation for minimally invasive surgery. ISCAS 2015: 1895 - [c33]An-Tia Xiao, Shiang-Ren Yang, Yuan-Hsiang Miao, Ching-Hwa Cheng, Jiun-In Guo:
A power-aware quad-voltage H.264 encoder chip for wireless panoramic endoscope applications. VLSI-DAT 2015: 1-4 - 2014
- [c32]Chun-Hsiang Peng, Ching-Hwa Cheng:
A panoramic endoscope design and implementation for Minimally Invasive Surgery. ISCAS 2014: 453-456 - 2013
- [j8]Miin-Shyue Shiau, Heng-Shou Hsu, Ching-Hwa Cheng, Hsiu-Hua Weng, Hong-Chong Wu, Don-Gey Liu:
Reduction of current mismatching in the switches-in-source CMOS charge pump. Microelectron. J. 44(12): 1296-1301 (2013) - [j7]Ching-Hwa Cheng:
Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor. VLSI Design 2013: 425105:1-425105:10 (2013) - [c31]Nan-Xiong Huang, Hsi Rong Han, Wen Tui Liao, Chih-Hung Huang, Wen Chun Wang, Miin-Shyue Shiau, Ching-Hwa Cheng, Hong-Chong Wu, Heng-Shou Hsu, Juin J. Liou, Shry-Sann Liao, Ruei-Cheng Sun, Guang-Bao Lu, Don-Gey Liu:
Integrated amorphous-Si TFT circuits for gate drivers on LCD panels. ASICON 2013: 1-4 - [c30]Ching-Hwa Cheng, Sheng-Wei Hsu, Jiun-In Guo:
A low-cost scalable Voltage-Frequency Adjustor for implementing low-power systems. ISCAS 2013: 655-658 - 2012
- [c29]Ching-Hwa Cheng, Jiun-In Guo:
A high-speed dual-phase processing pipelined domino circuit design with a built-in performance adjusting mechanism. VLSI-DAT 2012: 1-4 - 2011
- [c28]Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang, Ching-Hwa Cheng:
A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. ASP-DAC 2011: 73-74 - [c27]Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo:
Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism. ASP-DAC 2011: 85-86 - [c26]Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo:
A low-power management technique for high-performance domino circuits. ASP-DAC 2011: 93-94 - [c25]Ching-Hwa Cheng, Ming-Hsuan Wu, Pin-Jui Lai, Chia-Hao Ku:
A digitalized management mechanism for low-cost low-power multiple-voltage 3D designs. DSN Workshops 2011: 65-68 - [c24]Ching-Hwa Cheng, Chen-I Chung:
Built-in fine resolution clipping with calibration technique for high-speed testing by using wireless testers. DSN Workshops 2011: 81-84 - 2010
- [c23]Chen-I Chung, Jyun-Sian Jhou, Ching-Hwa Cheng:
Built-in self at-speed delay binning and calibration mechanism in wireless test platform. ASP-DAC 2010: 357-358 - [c22]Elone Lee, Feng-Tso Chien, Ching-Hwa Cheng, Jiun-In Guo:
Dynamic voltage domain assignment technique for low power performance manageable cell based design. ASP-DAC 2010: 359-360 - [c21]Chen-I Chung, Shuo-Wen Chang, Feng-Tso Chien, Ching-Hwa Cheng:
Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing. ASP-DAC 2010: 367-368
2000 – 2009
- 2009
- [j6]Ching-Hwa Cheng, Chin-Hsien Wang:
CKVdd: A Clock-Controlled Self-Stabilized Voltage Technique for Reducing Dynamic Power in CMOS Digital Circuits. IEICE Trans. Electron. 92-C(4): 391-400 (2009) - [j5]Chih-Da Chien, Cheng-An Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng:
A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications. ACM Trans. Design Autom. Electr. Syst. 14(1): 17:1-17:17 (2009) - [c20]Chin-Hsien Wang, Ching-Hwa Cheng, Jiun-In Guo:
CKVdd: a self-stabilization ramp-vdd technique for dynamic power reduction. ASP-DAC 2009: 93-94 - [c19]Ming-Chien Tsai, Ching-Hwa Cheng:
A full-synthesizable high-precision built-in delay time measurement circuit. ASP-DAC 2009: 123-124 - [c18]Chen-I Chung, Jyun-Sian Jhou, Ching-Hwa Cheng, Sih-Yan Li:
Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self Test. Asian Test Symposium 2009: 163-168 - [c17]Ching-Hwa Cheng, Chiou-Kou Tung, Shao-Hui Shieh, Yu-Cherng Hung:
Design High-Performance and Low-Power Adder Cores with Full-Swing Nodes for Embedded Systems. IIH-MSP 2009: 534-537 - [c16]Cheng-An Chien, Chih-Da Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng:
A Multi-standard Video Decoder for High Definition Video Applications. ISCAS 2009: 1933 - [c15]Chen-I Chung, Shuo-Wen Chang, Ching-Hwa Cheng:
Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing. ITC 2009: 1 - 2008
- [c14]Ming-Chien Tsai, Ching-Hwa Cheng, Chiou-Mao Yang:
An All-Digital High-Precision Built-In Delay Time Measurement Circuit. VTS 2008: 249-254 - 2007
- [j4]De-Sheng Chen, Chang-Tzu Lin, Yiwen Wang, Ching-Hwa Cheng:
Fixed-outline floorplanning using robust evolutionary search. Eng. Appl. Artif. Intell. 20(6): 821-830 (2007) - [c13]Chang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen, Yiwen Wang, Ching-Hwa Cheng:
Noise-Aware Floorplanning for Fast Power Supply Network Design. ISCAS 2007: 2028-2031 - [c12]Chih-Da Chien, Chien-Chang Lin, Yi-Hung Shih, He-Chun Chen, Chia-Jui Huang, Cheng-Yen Yu, Chih-Liang Chen, Ching-Hwa Cheng, Jiun-In Guo:
A 252kgate/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video Applications. ISSCC 2007: 282-603 - [c11]Hsiang-Hui Huang, Ching-Hwa Cheng:
Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit. VTS 2007: 110-118 - 2003
- [c10]Ching-Hwa Cheng:
Design Scan Test Strategy for Single Phase Dynamic Circuits. DFT 2003: 199- - 2002
- [j3]Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang:
Novel Techniques for Improving Testability Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2901-2912 (2002) - [c9]Ching-Hwa Cheng:
Adaptable Voltage Scan Testing of Charge-Sharing Faults for Domino Circuits. DFT 2002: 147-158 - 2001
- [j2]Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang:
Charge-sharing alleviation and detection for CMOS domino circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2): 266-280 (2001) - 2000
- [c8]Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang:
Novel techniques for improving testability analysis. Asian Test Symposium 2000: 392-397 - [c7]Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang:
Charge sharing fault analysis and testing for CMOS domino logic circuits. Asian Test Symposium 2000: 435-440 - [c6]Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone:
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits. DFT 2000: 329-337 - [c5]Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang:
Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. ICCAD 2000: 387-390 - [c4]Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone:
Charge Sharing Fault Analysis and Testing for CMOS Domino Logic Circuits. LATW 2000: 59-64
1990 – 1999
- 1999
- [c3]Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone:
Charge Sharing Fault Detection for CMOS Domino Logic Circuits. DFT 1999: 77-85 - 1997
- [j1]Yung-Yuan Chen, Shambhu J. Upadhyaya, Ching-Hwa Cheng:
A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors. IEEE Trans. Computers 46(12): 1363-1371 (1997) - 1995
- [c2]Yung-Yuan Chen, Ching-Hwa Cheng, Jwu-E Chen:
An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors. VLSI Design 1995: 349-354 - 1994
- [c1]Yung-Yuan Chen, Ching-Hwa Cheng, Yung-Ci Chou:
An Effective Reconfiguration Process for Fault-Tolerant VLSI/WSI Array Processors. EDCC 1994: 421-438
Coauthor Index
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