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2020 – today
- 2024
[j6]Erich Malan
, Valentino Peluso, Andrea Calimera, Enrico Macii, Paolo Montuschi:
Automatic Layer Freezing for Communication Efficiency in Cross-Device Federated Learning. IEEE Internet Things J. 11(4): 6072-6083 (2024)- 2023
- [j5]Erich Malan, Valentino Peluso, Andrea Calimera, Enrico Macii:
Communication-Efficient Federated Learning With Gradual Layer Freezing. IEEE Embed. Syst. Lett. 15(1): 25-28 (2023) - [c24]Giacomo Zema, Valentino Peluso, Andrea Calimera, Enrico Macii:
Concurrent Pipeline Stages Optimization for Embedded Keyword Spotting. AIIoT 2023: 427-433 - [c23]Erich Malan, Valentino Peluso, Andrea Calimera, Enrico Macii:
Enabling DVFS Side-Channel Attacks for Neural Network Fingerprinting in Edge Inference Services. ISLPED 2023: 1-6 - 2022
- [j4]Antonio Cipolletta, Valentino Peluso, Andrea Calimera, Matteo Poggi, Fabio Tosi, Filippo Aleotti, Stefano Mattoccia:
Energy-Quality Scalable Monocular Depth Estimation on Low-Power CPUs. IEEE Internet Things J. 9(1): 25-36 (2022) - [j3]Valentino Peluso, Antonio Cipolletta, Andrea Calimera, Matteo Poggi, Fabio Tosi, Filippo Aleotti, Stefano Mattoccia:
Monocular Depth Perception on Microcontrollers for Edge Applications. IEEE Trans. Circuits Syst. Video Technol. 32(3): 1524-1536 (2022) - 2021
- [j2]Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera:
TVFS: Topology Voltage Frequency Scaling for Reliable Embedded ConvNets. IEEE Trans. Circuits Syst. II Express Briefs 68(2): 672-676 (2021) - [c22]Luca Mocerino, Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Enrico Macii:
AdapTTA: Adaptive Test-Time Augmentation for Reliable Embedded ConvNets. VLSI-SoC 2021: 1-6 - [c21]Luca Mocerino, Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Enrico Macii:
On the Efficiency of AdapTTA: An Adaptive Test-Time Augmentation Strategy for Reliable Embedded ConvNets. VLSI-SoC (Selected Papers) 2021: 1-23 - [i2]Luca Mocerino, Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Enrico Macii:
Adaptive Test-Time Augmentation for Low-Power CPU. CoRR abs/2105.06183 (2021) - 2020
- [c20]Matteo Grimaldi, Valentino Peluso, Andrea Calimera:
EAST: Encoding-Aware Sparse Training for Deep Memory Compression of ConvNets. AICAS 2020: 233-237 - [c19]Valentino Peluso, Antonio Cipolletta, Andrea Calimera, Matteo Poggi, Fabio Tosi, Filippo Aleotti, Stefano Mattoccia:
Enabling monocular depth perception at the very edge. CVPR Workshops 2020: 1581-1583 - [c18]Valentino Peluso, Enrico Macii, Andrea Calimera:
Optimization Tools for ConvNets on the Edge. VLSI-SOC 2020: 204-205
2010 – 2019
- 2019
- [j1]Matteo Grimaldi, Valentino Peluso, Andrea Calimera:
Optimality Assessment of Memory-Bounded ConvNets Deployed on Resource-Constrained RISC Cores. IEEE Access 7: 152599-152611 (2019) - [c17]Valentino Peluso, Antonio Cipolletta, Andrea Calimera, Matteo Poggi, Fabio Tosi, Stefano Mattoccia:
Enabling Energy-Efficient Unsupervised Monocular Depth Estimation on ARMv7-Based Platforms. DATE 2019: 1703-1708 - [c16]Valentino Peluso, Antonio Cipolletta, Francesco Vaiana, Andrea Calimera:
Integer ConvNets on Embedded CPUs: Tools and Performance Assessment on the Cortex-A Cores. ICECS 2019: 598-601 - [c15]Valentino Peluso, Roberto Giorgio Rizzo, Antonio Cipolletta, Andrea Calimera:
Inference on the Edge: Performance Analysis of an Image Classification Task Using Off-The-Shelf CPUs and Open-Source ConvNets. SNAMS 2019: 454-459 - [c14]Valentino Peluso, Matteo Grimaldi, Andrea Calimera:
Arbitrary-Precision Convolutional Neural Networks on Low-Power IoT Processors. VLSI-SoC 2019: 142-147 - [i1]Matteo Grimaldi, Valentino Peluso, Andrea Calimera:
EAST: Encoding-Aware Sparse Training for Deep Memory Compression of ConvNets. CoRR abs/1912.10087 (2019) - 2018
- [c13]Daniele Jahier Pagliari, Valentino Peluso, Yukai Chen, Andrea Calimera, Enrico Macii, Massimo Poncino:
All-digital embedded meters for on-line power estimation. DATE 2018: 737-742 - [c12]Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto:
Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator. DATE 2018: 1151-1154 - [c11]Valentino Peluso, Andrea Calimera:
Scalable-effort ConvNets for multilevel classification. ICCAD 2018: 12 - [c10]Valentino Peluso, Andrea Calimera:
Weak-MAC: Arithmetic Relaxation for Dynamic Energy-Accuracy Scaling in ConvNets. ISCAS 2018: 1-5 - [c9]Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto:
Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS. ISCAS 2018: 1-5 - [c8]Valentino Peluso, Andrea Calimera:
Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis. VLSI-SoC (Selected Papers) 2018: 107-127 - [c7]Valentino Peluso, Andrea Calimera:
Energy-Driven Precision Scaling for Fixed-Point ConvNets. VLSI-SoC 2018: 113-118 - 2017
- [c6]Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Jun Zhou, Xin Liu:
Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS. VLSI-SoC 2017: 1-6 - [c5]Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Jun Zhou:
On the Efficiency of Early Bird Sampling (EBS) an Error Detection-Correction Scheme for Data-Driven Voltage Over-Scaling. VLSI-SoC (Selected Papers) 2017: 153-177 - 2016
- [c4]Valentino Peluso, Andrea Calimera, Enrico Macii, Massimo Alioto:
Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs. VLSI-SoC 2016: 1-6 - [c3]Valentino Peluso, Roberto Giorgio Rizzo, Andrea Calimera, Enrico Macii, Massimo Alioto:
Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping. VLSI-SoC (Selected Papers) 2016: 152-172 - 2015
- [c2]Alberto Bolzoni, Alessio La Bella, Davide Moschetta, Giulia Musacci, Giambattista Gruosso, Giancarlo Storti Gajani, Marco Aimo Boot, Luca Bellini, Alessio Canepa, Davide Cardella, Valentino Peluso, Paolo Guglielmi:
Object based modelling of hybrid electrical vehicle and power management control. RTSI 2015: 534-540
1990 – 1999
- 1998
- [c1]Augusto Manuel Marques, Valentino Peluso, Michiel Steyaert, Willy M. C. Sansen:
Analysis of the trade-off between bandwidth, resolution, and power in ΔΣ analog to digital converters. ICECS 1998: 153-156
Coauthor Index
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