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ORCIDRuijun Ma 0002
Person information
- affiliation: Anhui University of Science and Technology, Huainan, Anhui, China
Other persons with the same name
- Ruijun Ma — disambiguation page
- Ruijun Ma 0001
![[0000-0001-6876-8153]](https://dblp.org/img/orcid-mark.12x12.png "0000-0001-6876-8153")
— South China Agricultural University, College of Engineering, Guangzhou, China (and 2 more) - Ruijun Ma 0003 — South China Agricultural University, Guangzhou, Guangdong, China
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2020 – today
- 2025
[j10]Hui Xu, Xinzhong Xiao, Wenxin Huang, Ruijun Ma, Fuxin Tang, Pan Qi, Ye Yuan, Huaguo Liang:
Semi-supervised lithography hotspot detection based on feature fusion and residual attention. Integr. 104: 102472 (2025)- [j9]Hui Xu, Yong Xue, Yu Zhang, Xia Sun, Jiale Li, Ruijun Ma, Huaguo Liang, Zhengfeng Huang:
ESegNet-ILT: An end-to-end mask optimization method in VLSI design flow based on enhanced SegNet. Integr. 105: 102512 (2025) - [j8]Ruijun Ma, Stefan Holst, Hui Xu, Xiaoqing Wen, Senling Wang, Jiuqi Li, Aibin Yan:
Highly Defect Detectable and SEU-Resilient Robust Scan-Test-Aware Latch Design. IEEE Trans. Very Large Scale Integr. Syst. 33(2): 449-461 (2025) - [i1]Shaoqi Wei, Senling Wang, Hiroshi Kai, Yoshinobu Higami, Ruijun Ma, Tianming Ni, Xiaoqing Wen, Hiroshi Takahashi:
A Spatio-Temporal Graph Neural Networks Approach for Predicting Silent Data Corruption inducing Circuit-Level Faults. CoRR abs/2509.06289 (2025) - 2024
- [j7]Hui Xu, Xuewei Qin, Ruijun Ma, Chaoming Liu, Shuo Zhu, Jun Wang, Huaguo Liang:
A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches. J. Electron. Test. 40(1): 45-60 (2024) - [j6]Hui Xu, Shuo Zhu, Ruijun Ma, Zhengfeng Huang, Huaguo Liang, Haojie Sun, Chaoming Liu:
Design of novel low cost triple-node-upset self-recoverable hardened latch. Integr. 97: 102199 (2024) - [j5]Hui Xu, Yu Xia, Ruijun Ma, Huaguo Liang, Zhenfeng Huang:
A Low-Cost Triple-Node-Upset Self-Recovery Latch Design. J. Circuits Syst. Comput. 33(10) (2024) - [j4]Hui Xu, Chaoming Liu, Ruijun Ma, Tai Song, Zhengfeng Huang, Jun Wang, Xuewei Qin, Yu Xia:
Hardened latch designs based on the characteristic of transistor for mitigating multiple-node-upsets in harsh radiation environments. Microelectron. J. 143: 106031 (2024) - [j3]Hui Xu, Lin Tang, Ruijun Ma, Huaguo Liang, Zhengfeng Huang, Tianming Ni, Jiuqi Li, Xiaodong Ai:
A cost-effective and highly robust triple-node-upset self-recoverable latch design based on dual-output C-elements. Microelectron. J. 153: 106422 (2024) - [c4]Senling Wang, Shaoqi Wei, Hisashi Okamoto, Tatusya Nishikawa, Hiroshi Kai, Yoshinobu Higami, Hiroyuki Yotsuyanagi, Ruijun Ma, Tianming Ni, Hiroshi Takahashi, Xiaoqing Wen:
Test Point Selection for Multi-Cycle Logic BIST using Multivariate Temporal-Spatial GCNs. ITC-Asia 2024: 1-6 - 2023
- [j2]Hui Xu, Jing Zhou, Ruijun Ma, Huaguo Liang, Zhengfeng Huang, Chaoming Liu:
LQNTL: Low-overhead quadruple-node-upset self-recovery latch based on triple-mode redundancy. Integr. 91: 126-135 (2023) - [c3]Stefan Holst, Ruijun Ma, Xiaoqing Wen, Aibin Yan, Hui Xu:
BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell. ETS 2023: 1-6 - 2022
- [j1]Ruijun Ma, Stefan Holst, Xiaoqing Wen, Aibin Yan, Hui Xu:
Evaluation and Test of Production Defects in Hardened Latches. IEICE Trans. Inf. Syst. 105-D(5): 996-1009 (2022)
2010 – 2019
- 2019
- [c2]Ruijun Ma, Stefan Holst, Xiaoqing Wen, Aibin Yan, Hui Xu:
STAHL: A Novel Scan-Test-Aware Hardened Latch Design. ETS 2019: 1-6 - 2018
- [c1]Stefan Holst, Ruijun Ma, Xiaoqing Wen:
The impact of production defects on the soft-error tolerance of hardened latches. ETS 2018: 1-6
Coauthor Index
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