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ORCIDMasamitsu Tanaka
Person information
- affiliation: Nagoya University, Japan
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2020 – today
- 2024
[j16]Yosuke Ueno
, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura:
Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines. IEEE Comput. Archit. Lett. 23(1): 6-9 (2024)- [c12]Satoshi Kawakami, Yusuke Ohtusbo, Koji Inoue, Masamitsu Tanaka:
Late Breaking Results: Single Flux Quantum Based Brownian Circuits for Ultra-Law-Power Computing. DATE 2024: 1-2 - [i4]Yosuke Ueno, Satoshi Imamura, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura:
SFQ counter-based precomputation for large-scale cryogenic VQE machines. CoRR abs/2403.00363 (2024) - [i3]Yosuke Ueno, Satoshi Imamura, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura:
C3-VQA: Cryogenic Counter-based Co-processor for Variational Quantum Algorithms. CoRR abs/2409.07847 (2024) - 2023
- [c11]Masamitsu Tanaka, Yoshihiro Kitagawa, Tetsuro Satoh, Tsuyoshi Yamamoto:
High-Frequency Operation of Low-Power Single-Flux-Quantum Circuits Fabricated Using 250 A/cm2 Nb/AlOx/Nb Planarization Process. ICICDT 2023: 84-87 - [c10]Dongmoon Min, Junpyo Kim, Junhyuk Choi, Ilkwon Byun, Masamitsu Tanaka, Koji Inoue, Jangwoo Kim:
QIsim: Architecting 10+K Qubit QC Interfaces Toward Quantum Supremacy. ISCA 2023: 1:1-1:16 - [c9]Yasunari Suzuki, Yosuke Ueno, Wang Liao, Masamitsu Tanaka, Teruo Tanimoto:
Circuit designs for practical-scale fault-tolerant quantum computing. VLSI Technology and Circuits 2023: 1-2 - [i2]Yosuke Ueno, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura:
Inter-temperature Bandwidth Reduction in Cryogenic QAOA Machines. CoRR abs/2310.01630 (2023) - 2022
- [c8]Yosuke Ueno, Masaaki Kondo, Masamitsu Tanaka, Yasunari Suzuki, Yutaka Tabuchi:
QULATIS: A Quantum Error Correction Methodology toward Lattice Surgery. HPCA 2022: 274-287 - [c7]Ilkwon Byun, Junpyo Kim, Dongmoon Min, Ikki Nagaoka, Kosuke Fukumitsu, Iori Ishikawa, Teruo Tanimoto, Masamitsu Tanaka, Koji Inoue, Jangwoo Kim:
XQsim: modeling cross-technology control processors for 10+K qubit quantum computers. ISCA 2022: 366-382 - [c6]Iori Ishikawa, Ikki Nagaoka, Ryota Kashima, Koki Ishida, Kosuke Fukumitsu, Keitaro Oka, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Akira Fujimaki, Koji Inoue:
Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device. ISCAS 2022: 3547-3551 - [i1]Yosuke Ueno, Masaaki Kondo, Masamitsu Tanaka, Yasunari Suzuki, Yutaka Tabuchi:
NEO-QEC: Neural Network Enhanced Online Superconducting Decoder for Surface Codes. CoRR abs/2208.05758 (2022) - 2021
- [j15]Shuichi Nagasawa, Masamitsu Tanaka, Naoki Takeuchi, Yuki Yamanashi, Shigeyuki Miyajima, Fumihiro China, Taiki Yamae, Koki Yamazaki, Yuta Somei, Naonori Sega, Yoshinao Mizugaki, Hiroaki Myoren, Hirotaka Terai, Mutsuo Hidaka, Nobuyuki Yoshikawa, Akira Fujimaki:
Planarized Nb 4-Layer Fabrication Process for Superconducting Integrated Circuits and Its Fabricated Device Evaluation. IEICE Trans. Electron. 104-C(9): 435-445 (2021) - [j14]Koki Ishida, Ilkwon Byun, Ikki Nagaoka, Kosuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Jangwoo Kim, Koji Inoue:
Superconductor Computing for Neural Networks. IEEE Micro 41(3): 19-26 (2021) - [c5]Yosuke Ueno, Masaaki Kondo, Masamitsu Tanaka, Yasunari Suzuki, Yutaka Tabuchi:
QECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface Code. DAC 2021: 451-456 - 2020
- [c4]Koki Ishida, Ilkwon Byun, Ikki Nagaoka, Kosuke Fukumitsu, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Jangwoo Kim, Koji Inoue:
SuperNPU: An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices. MICRO 2020: 58-72 - [c3]Koki Ishida, Masamitsu Tanaka, Ikki Nagaoka, Takatsugu Ono, Satoshi Kawakami, Teruo Tanimoto, Akira Fujimaki, Koji Inoue:
32 GHz 6.5 mW Gate-Level-Pipelined 4-Bit Processor using Superconductor Single-Flux-Quantum Logic. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [c2]Ikki Nagaoka, Masamitsu Tanaka, Koji Inoue, Akira Fujimaki:
A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic. ISSCC 2019: 460-462 - 2018
- [j13]Koki Ishida, Masamitsu Tanaka, Takatsugu Ono, Koji Inoue:
Towards Ultra-High-Speed Cryogenic Single-Flux-Quantum Computing. IEICE Trans. Electron. 101-C(5): 359-369 (2018) - [j12]Kyosuke Sano, Masato Suzuki, Kohei Maruyama, Soya Taniguchi, Masamitsu Tanaka, Akira Fujimaki, Masumi Inoue, Nobuyuki Yoshikawa:
Thermally Assisted Superconductor Transistors for Josephson-CMOS Hybrid Memories. IEICE Trans. Electron. 101-C(5): 370-377 (2018) - [j11]Tomohiro Kamiya, Masamitsu Tanaka, Kyosuke Sano, Akira Fujimaki:
Energy/Space-Efficient Rapid Single-Flux-Quantum Circuits by Using π-Shifted Josephson Junctions. IEICE Trans. Electron. 101-C(5): 385-390 (2018) - 2016
- [j10]Ali Bozbey, Yuma Kita, Kyohei Kamiya, Misaki Kozaka, Masamitsu Tanaka, Takekazu Ishida, Akira Fujimaki:
Development of an Advanced Circuit Model for Superconducting Strip Line Detector Arrays. IEICE Trans. Electron. 99-C(6): 676-682 (2016) - [j9]Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi:
High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation. IEICE Trans. Electron. 99-C(6): 703-709 (2016) - [c1]Koki Ishida, Masamitsu Tanaka, Takatsugu Ono, Koji Inoue:
Single-flux-quantum cache memory architecture. ISOCC 2016: 105-106 - 2014
- [j8]Akira Fujimaki, Masamitsu Tanaka, Ryo Kasagi, Katsumi Takagi, Masakazu Okada, Yuhi Hayakawa, Kensuke Takata, Hiroyuki Akaike, Nobuyuki Yoshikawa, Shuichi Nagasawa, Kazuyoshi Takagi, Naofumi Takagi:
Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors. IEICE Trans. Electron. 97-C(3): 157-165 (2014) - [j7]Masamitsu Tanaka, Atsushi Kitayama, Masakazu Okada, Tomohito Kouketsu, Takumi Takinami, Masato Ito, Akira Fujimaki:
High-Speed Operation of 0.25-mV RSFQ Arithmetic Logic Unit Based on 10-kA/cm2 Nb Process Technology. IEICE Trans. Electron. 97-C(3): 166-172 (2014) - 2011
- [j6]Kazuyoshi Takagi, Yuki Ito, Shota Takeshima, Masamitsu Tanaka, Naofumi Takagi:
Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits. IEICE Trans. Electron. 94-C(3): 288-295 (2011) - 2010
- [j5]Naofumi Takagi, Masamitsu Tanaka:
Comparisons of Synchronous-Clocking SFQ Adders. IEICE Trans. Electron. 93-C(4): 429-434 (2010) - [j4]Masamitsu Tanaka, Koji Obata, Yuki Ito, Shota Takeshima, Motoki Sato, Kazuyoshi Takagi, Naofumi Takagi, Hiroyuki Akaike, Akira Fujimaki:
Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm. IEICE Trans. Electron. 93-C(4): 435-439 (2010) - [j3]Yuki Yamanashi, Toshiki Kainuma, Nobuyuki Yoshikawa, Irina Kataeva, Hiroyuki Akaike, Akira Fujimaki, Masamitsu Tanaka, Naofumi Takagi, Shuichi Nagasawa, Mutsuo Hidaka:
100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm2 Nb Multi-Layer Process. IEICE Trans. Electron. 93-C(4): 440-444 (2010)
2000 – 2009
- 2009
- [j2]Heejoung Park, Yuki Yamanashi, Nobuyuki Yoshikawa, Masamitsu Tanaka, Akira Fujimaki:
Design of fast digit-serial adders using SFQ logic circuits. IEICE Electron. Express 6(19): 1408-1413 (2009) - 2008
- [j1]Akira Fujimaki, Masamitsu Tanaka, Takahiro Yamada, Yuki Yamanashi, Heejoung Park, Nobuyuki Yoshikawa:
Bit-Serial Single Flux Quantum Microprocessor CORE. IEICE Trans. Electron. 91-C(3): 342-349 (2008)
Coauthor Index
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