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ORCIDPritam Bhattacharjee
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2020 – today
- 2024
[c8]Priyanka J, Pritam Bhattacharjee, Alak Majumder:
Exploring the Application of Variable Frequency Clock as the Constituent of OCT. iSES 2024: 195-199- [c7]Priyanka J, Ankita Deb, Pritam Bhattacharjee, Alak Majumder:
An Algorithmic Approach of Generating a VFC of Low Average Frequency Ramp. iSES 2024: 220-223 - [c6]Vipin Kumar Singh, Vijay Pratap Yadav, Tika Ram Pokhrel, Pritam Bhattacharjee, Alak Majumder:
A Method of Variable Frequency Clock Generation. iSES 2024: 251-254 - [c5]Pritam Bhattacharjee, Alak Majumder:
Design of VFC with Programmable Frequency Ramp to control on-chip switching current profile. VLSID 2024: 587-592 - 2023
- [c4]Pritam Bhattacharjee, G. Naveen Goud, Vipin Kumar Singh, Vijay Pratap Yadav, Abir J. Mondal, Alak Majumder:
Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS. RADIOELEKTRONIKA 2023: 1-6 - 2022
- [j5]Pritam Bhattacharjee
, Prerna Rana, Bidyut K. Bhattacharyya, Alak Majumder:
Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1704-1715 (2022) - 2021
- [j4]Pritam Bhattacharjee, Bidyut K. Bhattacharyya, Alak Majumder:
A Vector-Controlled Variable Delay Circuit to Develop Near-Symmetric Output Rise/Fall Time. Circuits Syst. Signal Process. 40(4): 1569-1588 (2021)
2010 – 2019
- 2019
- [j3]Pritam Bhattacharjee, Alak Majumder:
A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application. J. Circuits Syst. Comput. 28(7): 1950108:1-1950108:26 (2019) - 2018
- [j2]Alak Majumder, Pritam Bhattacharjee, Tushar Dhabal Das:
A Novel Gating Approach to Alleviate Power and Ground Noise in Silicon Chips. J. Circuits Syst. Comput. 27(9): 1850146:1-1850146:9 (2018) - [i2]Pritam Bhattacharjee, Bipasha Nath, Alak Majumder:
LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications. CoRR abs/1805.07409 (2018) - [i1]Dhiraj Sarkar, Pritam Bhattacharjee, Alak Majumder:
Data-Dependent Clock Gating approach for Low Power Sequential System. CoRR abs/1806.02271 (2018) - 2017
- [j1]Pritam Bhattacharjee, Kunal Das, Arijit Dey, Debashis De, Swarnendu Kumar Chakraborty:
Estimation of Power Dissipation in Ternary Quantum Dot Cellular Automata Cell. J. Low Power Electron. 13(2): 231-239 (2017) - [c3]Alak Majumder, Pritam Bhattacharjee:
Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip. iNIS 2017: 224-228 - 2016
- [c2]Pritam Bhattacharjee, Alak Majumder:
LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder. iNIS 2016: 250-254 - [c1]Pritam Bhattacharjee, Alak Majumder, Tushar Dhabal Das:
A 90 nm leakage control transistor based clock gating for low power flip flop applications. MWSCAS 2016: 1-4
Coauthor Index
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