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2020 – today
- 2024
[i5]Dhruv Gajaria, Kyle Kuan, Tosiron Adegbija:
SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning. CoRR abs/2407.19604 (2024)- 2022
- [c6]Kyle Kuan, Tosiron Adegbija:
A Study of STTRAM-based Page Walker Caches for Energy-Efficient Address Translation. ISVLSI 2022: 74-79 - 2021
- [b1]Kyle Kuan:
Advancing STTRAM Caches for Runtime Adaptable Energy-Efficient Microarchitectures. University of Arizona, Tucson, USA, 2021 - 2020
- [j2]Kyle Kuan
, Tosiron Adegbija:
Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1328-1339 (2020) - [c5]Kyle Kuan, Tosiron Adegbija:
A Study of Runtime Adaptive Prefetching for STTRAM L1 Caches. ICCD 2020: 247-254 - [i4]Kyle Kuan, Tosiron Adegbija:
A Study of Runtime Adaptive Prefetching for STTRAM L1 Caches. CoRR abs/2009.11442 (2020)
2010 – 2019
- 2019
- [j1]Kyle Kuan, Tosiron Adegbija:
HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems. IEEE Trans. Computers 68(11): 1623-1634 (2019) - [c4]Kyle Kuan, Tosiron Adegbija:
MirrorCache: An Energy-Efficient Relaxed Retention L1 STTRAM Cache. ACM Great Lakes Symposium on VLSI 2019: 299-302 - [c3]Dhruv Gajaria, Kyle Kuan, Tosiron Adegbija:
SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning. IGSC 2019: 1-7 - [c2]Kyle Kuan, Tosiron Adegbija:
Energy and Performance Analysis of STTRAM Caches for Mobile Applications. MCSoC 2019: 257-264 - [i3]Kyle Kuan, Tosiron Adegbija:
Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design. CoRR abs/1904.09363 (2019) - [i2]Kyle Kuan, Tosiron Adegbija:
HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems. CoRR abs/1905.07511 (2019) - [i1]Kyle Kuan, Tosiron Adegbija:
Energy and Performance Analysis of STTRAM Caches for Mobile Applications. CoRR abs/1908.04744 (2019) - 2018
- [c1]Kyle Kuan, Tosiron Adegbija:
LARS: Logically adaptable retention time STT-RAM cache for embedded systems. DATE 2018: 461-466
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