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ORCIDYuan Pu 0001
Person information
- unicode name: 蒲渊
- affiliation: Chinese University of Hong Kong (CUHK), Department of Computer Science and Engineering, Sha Tin, Hong Kong
Other persons with the same name
- Yuan Pu — disambiguation page
- Yuan Pu 0002
![[0009-0008-4227-1833]](https://dblp.org/img/orcid-mark.12x12.png "0009-0008-4227-1833")
— Yale University, School of Medicine, New Haven, CT, USA
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2020 – today
- 2025
[j2]Ziyi Wang, Wenqian Zhao, Yuan Pu, Lei Chen, Wilson W. K. Thong, Weihua Sheng, Tsung-Yi Ho, Bei Yu:
ParSGCN: Bridging the Gap Between Emulation Partitioning and Scheduling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(3): 1180-1192 (2025)- [c8]Yuan Pu, Fangzhou Liu, Zhuolun He, Keren Zhu, Rongliang Fu, Ziyi Wang, Tsung-Yi Ho, Bei Yu:
HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning. ISPD 2025: 116-124 - [i2]Haoyuan Wu, Haisheng Zheng, Yuan Pu, Bei Yu:
Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment. CoRR abs/2502.12732 (2025) - 2024
- [c7]Yuan Pu, Fangzhou Liu, Yu Zhang, Zhuolun He, Yibo Lin, Kai-Yuan Chao, Bei Yu:
Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs. DAC 2024: 116:1-116:6 - [c6]Hongduo Liu, Peng Xu, Yuan Pu, Lihao Yin, Hui-Ling Zhen, Mingxuan Yuan, Tsung-Yi Ho, Bei Yu:
NeuroSelect: Learning to Select Clauses in SAT Solvers. DAC 2024: 131:1-131:6 - [c5]Yuan Pu, Zhuolun He, Tairu Qiu, Haoyuan Wu, Bei Yu:
Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA. ICCAD 2024: 116:1-116:9 - [c4]Yu Zhang, Yuan Pu, Fangzhou Liu, Peiyu Liao, Kai-Yuan Chao, Keren Zhu, Yibo Lin, Bei Yu:
Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells. ISPD 2024: 161-168 - [c3]Yuan Pu, Tinghuan Chen, Zhuolun He, Chen Bai, Haisheng Zheng, Yibo Lin, Bei Yu:
IncreMacro: Incremental Macro Placement Refinement. ISPD 2024: 169-176 - [i1]Yuan Pu, Zhuolun He, Tairu Qiu, Haoyuan Wu, Bei Yu:
Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA. CoRR abs/2407.15353 (2024) - 2023
- [j1]Siting Liu, Yuan Pu, Peiyu Liao, Hongzhong Wu, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu:
FastGR: Global Routing on CPU-GPU With Heterogeneous Task Graph Scheduler. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7): 2317-2330 (2023) - [c2]Ziyi Wang, Siting Liu, Yuan Pu, Song Chen, Tsung-Yi Ho, Bei Yu:
Restructure-Tolerant Timing Prediction via Multimodal Fusion. DAC 2023: 1-6 - [c1]Siting Liu, Yuan Pu, Peiyu Liao, Hongzhong Wu, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu:
FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler (Extended Abstract). IJCAI 2023: 6458-6462
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