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ORCIDBei Yu 0001
Person information
- affiliation: Chinese University of Hong Kong, Department of Computer Science and Engineering, Hong Kong
- affiliation (PhD 2014): University of Texas at Austin, Department of Electrical and Computer Engineering, TX, USA
Other persons with the same name
- Bei Yu — disambiguation page
- Bei Yu 0002
![[0000-0001-5425-0011]](https://dblp.org/img/orcid-mark.12x12.png "0000-0001-5425-0011")
— Syracuse University, School of Information Studies, Syracuse, NY, USA (and 2 more) - Bei Yu 0003 — National University of Singapore, Singapore-MIT Alliance, School of Computing, Singapore
- Bei Yu 0004 — State Grid Electronic Commerce Co., Ltd, State Grid Huitong Jincai, State Grid Financial Technology Group, Beijing, China
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2020 – today
- 2024
[j102]Xiaoliu Luo, Zhuotao Tian, Taiping Zhang, Bei Yu, Yuan Yan Tang, Jiaya Jia:
PFENet++: Boosting Few-Shot Semantic Segmentation With the Noise-Filtered Context-Aware Prior Mask. IEEE Trans. Pattern Anal. Mach. Intell. 46(2): 1273-1289 (2024)- [j101]Xiaoxiao Liang, Yikang Ouyang, Haoyu Yang, Bei Yu, Yuzhe Ma:
RL-OPC: Mask Optimization With Deep Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(1): 340-351 (2024) - [j100]Yang Bai, Xufeng Yao, Qi Sun, Wenqian Zhao, Shixin Chen, Zixiao Wang, Bei Yu:
GTCO: Graph and Tensor Co-Design for Transformer-Based Image Recognition on Tensor Cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 586-599 (2024) - [j99]Zhaoting Chen, Junzhe Cai, Changhao Yan, Zhaori Bi, Yuzhe Ma, Bei Yu, Wenchuang Walter Hu, Dian Zhou, Xuan Zeng:
pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter Adjustment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 667-680 (2024) - [j98]Binwu Zhu, Su Zheng, Ziyang Yu, Guojin Chen, Yuzhe Ma, Fan Yang, Bei Yu, Martin D. F. Wong:
L2O-ILT: Learning to Optimize Inverse Lithography Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(3): 944-955 (2024) - [j97]Peiyu Liao, Yuxuan Zhao, Dawei Guo, Yibo Lin, Bei Yu:
Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(6): 1624-1637 (2024) - [j96]Shixin Chen, Shanyi Li, Zhen Zhuang, Su Zheng, Zheng Liang, Tsung-Yi Ho, Bei Yu, Alberto L. Sangiovanni-Vincentelli:
Floorplet: Performance-Aware Floorplan Framework for Chiplet Integration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(6): 1638-1649 (2024) - [j95]Guojin Chen, Zixiao Wang, Bei Yu, David Z. Pan, Martin D. F. Wong:
Ultrafast Source Mask Optimization via Conditional Discrete Diffusion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(7): 2140-2150 (2024) - [j94]Wenqian Zhao, Xufeng Yao, Shuo Yin, Yang Bai, Ziyang Yu, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
AdaOPC 2.0: Enhanced Adaptive Mask Optimization Framework for via Layers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(9): 2674-2686 (2024) - [j93]Yuyang Ye, Tinghuan Chen, Yifei Gao, Hao Yan, Bei Yu, Longxing Shi:
Timing-Driven Technology Mapping Approximation Based on Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(9): 2755-2768 (2024) - [j92]Haoyuan Wu, Zhuolun He, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, Bei Yu:
ChatEDA: A Large Language Model Powered Autonomous Agent for EDA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(10): 3184-3197 (2024) - [j91]Yuyang Ye, Tinghuan Chen, Zicheng Wang, Hao Yan, Bei Yu, Longxing Shi:
Fast and Accurate Aging-Aware Cell Timing Model via Graph Learning. IEEE Trans. Circuits Syst. II Express Briefs 71(1): 156-160 (2024) - [j90]Yuzhe Ma, Xufeng Yao, Ran Chen, Ruiyu Li, Xiaoyong Shen, Bei Yu:
Small is Beautiful: Compressing Deep Neural Networks for Partial Domain Adaptation. IEEE Trans. Neural Networks Learn. Syst. 35(3): 3575-3585 (2024) - [j89]Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration. ACM Trans. Design Autom. Electr. Syst. 29(1): 20:1-20:23 (2024) - [j88]Hongduo Liu, Yijian Qian, Youqiang Liang, Bin Zhang, Zhaohan Liu, Tao He, Wenqian Zhao, Jiangbo Lu, Bei Yu:
A High-Performance Accelerator for Real-Time Super-Resolution on Edge FPGAs. ACM Trans. Design Autom. Electr. Syst. 29(3): 53:1-53:25 (2024) - [j87]Bo Yang, Qi Xu, Hao Geng, Song Chen, Bei Yu, Yi Kang:
Floorplanning with Edge-aware Graph Attention Network and Hindsight Experience Replay. ACM Trans. Design Autom. Electr. Syst. 29(3): 56:1-56:17 (2024) - [c187]Chen Bai, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
Towards Automated RISC-V Microarchitecture Design with Reinforcement Learning. AAAI 2024: 12-20 - [c186]Haoyuan Wu, Xinyun Zhang, Peng Xu, Peiyu Liao, Xufeng Yao, Bei Yu:
p-Laplacian Adaptation for Generative Pre-trained Vision-Language Models. AAAI 2024: 6003-6011 - [c185]Xufeng Yao, Fanbin Lu, Yuechen Zhang, Xinyun Zhang, Wenqian Zhao, Bei Yu:
Progressively Knowledge Distillation via Re-parameterizing Diffusion Reverse Process. AAAI 2024: 16425-16432 - [c184]Xingquan Li, Zengrong Huang, Simin Tao, Zhipeng Huang, Chunan Zhuang, Hao Wang, Yifan Li, Yihang Qiu, Guojie Luo, Huawei Li, Haihua Shen, Mingyu Chen, Dongbo Bu, Wenxing Zhu, Ye Cai, Xiaoming Xiong, Ying Jiang, Yi Heng, Peng Zhang, Bei Yu, Biwei Xie, Yungang Bao:
iEDA: An Open-source infrastructure of EDA. ASPDAC 2024: 77-82 - [c183]Xingquan Li, Simin Tao, Shijian Chen, Zhisheng Zeng, Zhipeng Huang, Hongxi Wu, Weiguo Li, Zengrong Huang, Liwei Ni, Xueyan Zhao, He Liu, Shuaiying Long, Ruizhi Liu, Xiaoze Lin, Bo Yang, Fuxing Huang, Zonglin Yang, Yihang Qiu, Zheqing Shao, Jikang Liu, Yuyao Liang, Biwei Xie, Yungang Bao, Bei Yu:
iPD: An Open-source intelligent Physical Design Toolchain. ASPDAC 2024: 83-88 - [c182]Shixin Chen, Su Zheng, Chen Bai, Wenqian Zhao, Shuo Yin, Yang Bai, Bei Yu:
SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design. ASPDAC 2024: 207-212 - [c181]Peng Xu, Jintao Li, Tsung-Yi Ho, Bei Yu, Keren Zhu:
Performance-Driven Analog Layout Automation: Current Status and Future Directions (Invited Paper). ASPDAC 2024: 679-685 - [c180]Haisheng Zheng, Zhuolun He, Fangzhou Liu, Zehua Pei, Bei Yu:
LSTP: A Logic Synthesis Timing Predictor. ASPDAC 2024: 728-733 - [c179]Ping Zhang, Pengju Yao, Xingquan Li, Bei Yu, Wenxing Zhu:
V-GR: 3D Global Routing with Via Minimization and Multi-Strategy Rip-up and Rerouting. ASPDAC 2024: 963-968 - [c178]Jiequan Cui, Beier Zhu, Xin Wen, Xiaojuan Qi, Bei Yu, Hanwang Zhang:
Classes Are Not Equal: An Empirical Study on Image Recognition Fairness. CVPR 2024: 23283-23292 - [c177]Hongduo Liu, Peiyu Liao, Junhua Huang, Hui-Ling Zhen, Mingxuan Yuan, Tsung-Yi Ho, Bei Yu:
Parallel Gröbner Basis Rewriting and Memory Optimization for Efficient Multiplier Verification. DATE 2024: 1-6 - [c176]Fangzhou Liu, Zehua Pei, Ziyang Yu, Haisheng Zheng, Zhuolun He, Tinghuan Chen, Bei Yu:
CBTune: Contextual Bandit Tuning for Logic Synthesis. DATE 2024: 1-6 - [c175]Shan Shen, Dingcheng Yang, Yuyang Xie, Chunyan Pei, Bei Yu, Wenjian Yu:
Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs. ACM Great Lakes Symposium on VLSI 2024: 440-445 - [c174]Zehua Pei, Hui-Ling Zhen, Mingxuan Yuan, Yu Huang, Bei Yu:
BetterV: Controlled Verilog Generation with Discriminative Guidance. ICML 2024 - [c173]Lancheng Zou, Wenqian Zhao, Shuo Yin, Chen Bai, Qi Sun, Bei Yu:
BiE: Bi-Exponent Block Floating-Point for Large Language Models Quantization. ICML 2024 - [c172]Shuo Yin, Wenqian Zhao, Li Xie, Hong Chen, Yuzhe Ma, Tsung-Yi Ho, Bei Yu:
FuILT: Full Chip ILT System With Boundary Healing. ISPD 2024: 13-20 - [c171]Zhuolun He, Bei Yu:
Large Language Models for EDA: Future or Mirage? ISPD 2024: 65-66 - [c170]Siting Liu, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, Bei Yu, Martin D. F. Wong:
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs. ISPD 2024: 75-82 - [c169]Yu Zhang, Yuan Pu, Fangzhou Liu, Peiyu Liao, Kai-Yuan Chao, Keren Zhu, Yibo Lin, Bei Yu:
Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells. ISPD 2024: 161-168 - [c168]Yuan Pu, Tinghuan Chen, Zhuolun He, Chen Bai, Haisheng Zheng, Yibo Lin, Bei Yu:
IncreMacro: Incremental Macro Placement Refinement. ISPD 2024: 169-176 - [i80]Haoyuan Wu, Haisheng Zheng, Bei Yu:
Parameter-Efficient Sparsity Crafting from Dense to Mixture-of-Experts for Instruction Tuning on General Tasks. CoRR abs/2401.02731 (2024) - [i79]Zehua Pei, Hui-Ling Zhen, Mingxuan Yuan, Yu Huang, Bei Yu:
BetterV: Controlled Verilog Generation with Discriminative Guidance. CoRR abs/2402.03375 (2024) - [i78]Yu Zhang, Hui-Ling Zhen, Zehua Pei, Yingzhao Lian, Lihao Yin, Mingxuan Yuan, Bei Yu:
SoLA: Solver-Layer Adaption of LLM for Better Logic Reasoning. CoRR abs/2402.11903 (2024) - [i77]Jiequan Cui, Beier Zhu, Xin Wen, Xiaojuan Qi, Bei Yu, Hanwang Zhang:
Classes Are Not Equal: An Empirical Study on Image Recognition Fairness. CoRR abs/2402.18133 (2024) - [i76]Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yun Liang, Yibo Lin, Jinwei Liu, Yi Liu, Guojie Luo, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Evangeline F. Y. Young, Bei Yu, Mingxuan Yuan, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou:
The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. CoRR abs/2403.07257 (2024) - [i75]Yuyang Ye, Peng Xu, Lizheng Ren, Tinghuan Chen, Hao Yan, Bei Yu, Longxing Shi:
Learning-driven Physically-aware Large-scale Circuit Gate Sizing. CoRR abs/2403.08193 (2024) - [i74]Yuxuan Zhao, Peiyu Liao, Siting Liu, Jiaxi Jiang, Yibo Lin, Bei Yu:
Analytical Heterogeneous Die-to-Die 3D Placement with Macros. CoRR abs/2403.09070 (2024) - [i73]Xufeng Yao, Haoyang Li, Tsz Ho Chan, Wenyi Xiao, Mingxuan Yuan, Yu Huang, Lei Chen, Bei Yu:
HDLdebugger: Streamlining HDL debugging with Large Language Models. CoRR abs/2403.11671 (2024) - [i72]Zixiao Wang, Yunheng Shen, Xufeng Yao, Wenqian Zhao, Yang Bai, Farzan Farnia, Bei Yu:
ChatPattern: Layout Pattern Customization via Natural Language. CoRR abs/2403.15434 (2024) - [i71]Xiaoxiao Liang, Haoyu Yang, Kang Liu, Bei Yu, Yuzhe Ma:
CAMO: Correlation-Aware Mask Optimization with Modulated Reinforcement Learning. CoRR abs/2404.00980 (2024) - [i70]Tong Qiao, Jianlei Yang, Yingjie Qi, Ao Zhou, Chen Bai, Bei Yu, Weisheng Zhao, Chunming Hu:
GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration. CoRR abs/2404.09544 (2024) - [i69]Guojin Chen, Keren Zhu, Seunggeun Kim, Hanqing Zhu, Yao Lai, Bei Yu, David Z. Pan:
LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation. CoRR abs/2406.05250 (2024) - [i68]Zixiao Wang, Jingwei Zhang, Wenqian Zhao, Farzan Farnia, Bei Yu:
MoreauPruner: Robust Pruning of Large Language Models against Weight Perturbations. CoRR abs/2406.07017 (2024) - [i67]Yuan Pu, Zhuolun He, Tairu Qiu, Haoyuan Wu, Bei Yu:
Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA. CoRR abs/2407.15353 (2024) - [i66]Guojin Chen, Haoyu Yang, Haoxing Ren, Bei Yu, David Z. Pan:
Differentiable Edge-based OPC. CoRR abs/2408.08969 (2024) - [i65]Guojin Chen, Haoyu Yang, Bei Yu, Haoxing Ren:
Intelligent OPC Engineer Assistant for Semiconductor Manufacturing. CoRR abs/2408.12775 (2024) - [i64]Xufeng Yao, Yiwen Wang, Xing Li, Yingzhao Lian, Ran Chen, Lei Chen, Mingxuan Yuan, Hong Xu, Bei Yu:
RTLRewriter: Methodologies for Large Models aided RTL Code Optimization. CoRR abs/2409.11414 (2024) - [i63]Guojin Chen, Hao Geng, Bei Yu, David Z. Pan:
Open-Source Differentiable Lithography Imaging Framework. CoRR abs/2409.15306 (2024) - 2023
- [j86]Ulf Schlichtmann, Bing Li, Bei Yu, Raviv Gal:
Guest Editors' Introduction: Special Issue on Machine Learning for CAD/EDA. IEEE Des. Test 40(1): 5-7 (2023) - [j85]Tinghuan Chen, Grace Li Zhang, Bei Yu, Bing Li, Ulf Schlichtmann:
Machine Learning in Advanced IC Design: A Methodological Survey. IEEE Des. Test 40(1): 17-33 (2023) - [j84]Xiaogang Xu, Yi Wang, Liwei Wang, Bei Yu, Jiaya Jia:
Conditional Temporal Variational AutoEncoder for Action Video Prediction. Int. J. Comput. Vis. 131(10): 2699-2722 (2023) - [j83]Zhuotao Tian, Pengguang Chen, Xin Lai, Li Jiang, Shu Liu, Hengshuang Zhao, Bei Yu, Ming-Chang Yang, Jiaya Jia:
Adaptive Perspective Distillation for Semantic Segmentation. IEEE Trans. Pattern Anal. Mach. Intell. 45(2): 1372-1387 (2023) - [j82]Yilun Chen, Shijia Huang, Shu Liu, Bei Yu, Jiaya Jia:
DSGN++: Exploiting Visual-Spatial Relation for Stereo-Based 3D Detectors. IEEE Trans. Pattern Anal. Mach. Intell. 45(4): 4416-4429 (2023) - [j81]Qi Xu, Junpeng Wang, Bo Yuan, Qi Sun, Song Chen, Bei Yu, Yi Kang, Feng Wu:
Reliability-Driven Memristive Crossbar Design in Neuromorphic Computing Systems. IEEE Trans Autom. Sci. Eng. 20(1): 74-87 (2023) - [j80]Hao Geng, Tinghuan Chen, Yuzhe Ma, Binwu Zhu, Bei Yu:
PTPT: Physical Design Tool Parameter Tuning via Multi-Objective Bayesian Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 178-189 (2023) - [j79]Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu:
McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 243-256 (2023) - [j78]Ziyang Yu, Guojin Chen, Yuzhe Ma, Bei Yu:
A GPU-Enabled Level-Set Method for Mask Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 594-605 (2023) - [j77]Ran Chen, Shoubo Hu, Zhitang Chen, Shengyu Zhu, Bei Yu, Pengyun Li, Cheng Chen, Yu Huang, Jianye Hao:
A Unified Framework for Layout Pattern Analysis With Deep Causal Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4): 1199-1211 (2023) - [j76]Siting Liu, Yuan Pu, Peiyu Liao, Hongzhong Wu, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu:
FastGR: Global Routing on CPU-GPU With Heterogeneous Task Graph Scheduler. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7): 2317-2330 (2023) - [j75]Ziyi Wang, Zhuolun He, Chen Bai, Haoyu Yang, Bei Yu:
Efficient Arithmetic Block Identification With Graph Learning and Network-Flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8): 2591-2603 (2023) - [j74]Wenqian Zhao, Yang Bai, Qi Sun, Wenbo Li, Haisheng Zheng, Nianjuan Jiang, Jiangbo Lu, Bei Yu, Martin D. F. Wong:
A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(10): 3210-3223 (2023) - [j73]Peiyu Liao, Dawei Guo, Zizheng Guo, Siting Liu, Yibo Lin, Bei Yu:
DREAMPlace 4.0: Timing-Driven Placement With Momentum-Based Net Weighting and Lagrangian-Based Refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(10): 3374-3387 (2023) - [j72]Tinghuan Chen, Silu Xiong, Huan He, Bei Yu:
TRouter: Thermal-Driven PCB Routing via Nonlocal Crisscross Attention Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(10): 3388-3401 (2023) - [j71]Ziyang Yu, Peiyu Liao, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
CTM-SRAF: Continuous Transmission Mask-Based Constraint-Aware Subresolution Assist Feature Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(10): 3402-3411 (2023) - [j70]Yuyang Ye, Tinghuan Chen, Yifei Gao, Hao Yan, Bei Yu, Longxing Shi:
Aging-Aware Critical Path Selection via Graph Attention Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 5006-5019 (2023) - [j69]Guojin Chen, Ziyang Yu, Hongduo Liu, Yuzhe Ma, Bei Yu:
DevelSet: Deep Neural Level Set for Instant Mask Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 5020-5033 (2023) - [j68]Su Zheng, Hao Geng, Chen Bai, Bei Yu, Martin D. F. Wong:
Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization. ACM Trans. Design Autom. Electr. Syst. 28(5): 74:1-74:23 (2023) - [j67]Binwu Zhu, Xinyun Zhang, Yibo Lin, Bei Yu, Martin D. F. Wong:
DRC-SG 2.0: Efficient Design Rule Checking Script Generation via Key Information Extraction. ACM Trans. Design Autom. Electr. Syst. 28(5): 80:1-80:18 (2023) - [c167]Yuxuan Zhao, Qi Sun, Zhuolun He, Yang Bai, Bei Yu:
AutoGraph: Optimizing DNN Computation Graph for Parallel GPU Kernel Execution. AAAI 2023: 11354-11362 - [c166]Su Zheng, Bei Yu, Martin D. F. Wong:
OpenILT: An Open Source Inverse Lithography Technique Framework (Invited Paper). ASICON 2023: 1-4 - [c165]Jianwang Zhai, Yici Cai, Bei Yu:
Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning. ASP-DAC 2023: 302-307 - [c164]Yuyang Ye, Tinghuan Chen, Yifei Gao, Hao Yan, Bei Yu, Longxing Shi:
Graph-Learning-Driven Path-Based Timing Analysis Results Predictor from Graph-Based Timing Analysis. ASP-DAC 2023: 547-552 - [c163]Hao Geng, Qi Sun, Tinghuan Chen, Qi Xu, Tsung-Yi Ho, Bei Yu:
Mixed-Type Wafer Failure Pattern Recognition. ASP-DAC 2023: 727-732 - [c162]Guojin Chen, Zehua Pei, Haoyu Yang, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields. DAC 2023: 1-6 - [c161]Zhuolun He, Yihang Zuo, Jiaxi Jiang, Haisheng Zheng, Yuzhe Ma, Bei Yu:
OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration. DAC 2023: 1-6 - [c160]Peiyu Liao, Hongduo Liu, Yibo Lin, Bei Yu, Martin D. F. Wong:
On a Moreau Envelope Wirelength Model for Analytical Global Placement. DAC 2023: 1-6 - [c159]Hongduo Liu, Peiyu Liao, Mengchuan Zou, Bowen Pang, Xijun Li, Mingxuan Yuan, Tsung-Yi Ho, Bei Yu:
Layout Decomposition via Boolean Satisfiability. DAC 2023: 1-6 - [c158]Siting Liu, Ziyi Wang, Fangzhou Liu, Yibo Lin, Bei Yu, Martin D. F. Wong:
Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement. DAC 2023: 1-6 - [c157]Shuyuan Sun, Fan Yang, Bei Yu, Li Shang, Xuan Zeng:
Efficient ILT via Multi-level Lithography Simulation. DAC 2023: 1-6 - [c156]Ziyi Wang, Siting Liu, Yuan Pu, Song Chen, Tsung-Yi Ho, Bei Yu:
Restructure-Tolerant Timing Prediction via Multimodal Fusion. DAC 2023: 1-6 - [c155]Zixiao Wang, Yunheng Shen, Wenqian Zhao, Yang Bai, Guojin Chen, Farzan Farnia, Bei Yu:
DiffPattern: Layout Pattern Generation via Discrete Diffusion. DAC 2023: 1-6 - [c154]Yu Zhang, Yifan Chen, Zhonglin Xie, Hong Xu, Zaiwen Wen, Yibo Lin, Bei Yu:
LRSDP: Low-Rank SDP for Triple Patterning Lithography Layout Decomposition. DAC 2023: 1-6 - [c153]Su Zheng, Lancheng Zou, Siting Liu, Yibo Lin, Bei Yu, Martin D. F. Wong:
Mitigating Distribution Shift for Congestion Optimization in Global Placement. DAC 2023: 1-6 - [c152]Rongliang Fu, Junying Huang, Mengmeng Wang, Nobuyuki Yoshikawa, Bei Yu, Tsung-Yi Ho, Olivia Chen:
BOMIG: A Majority Logic Synthesis Framework for AQFP Logic. DATE 2023: 1-2 - [c151]Yuyang Ye, Tinghuan Chen, Yifei Gao, Hao Yan, Bei Yu, Longxing Shi:
Fast and Accurate Wire Timing Estimation Based on Graph Learning. DATE 2023: 1-6 - [c150]Wei Zhong, Zhenhua Feng, Zhuolun He, Weimin Wang, Yuzhe Ma, Bei Yu:
Efficient Design Rule Checking with GPU Acceleration. DATE 2023: 1-2 - [c149]Yang Bai, Wenqian Zhao, Shuo Yin, Zixiao Wang, Bei Yu:
ATFormer: A Learned Performance Model with Transfer Learning Across Devices for Deep Learning Tensor Programs. EMNLP 2023: 4102-4116 - [c148]Chen Bai, Xuechao Wei, Youwei Zhuo, Yi Cai, Hongzhong Zheng, Bei Yu, Yuan Xie:
Klotski: DNN Model Orchestration Framework for Dataflow Architecture Accelerators. ICCAD 2023: 1-9 - [c147]Rongliang Fu, Olivia Chen, Bei Yu, Nobuyuki Yoshikawa, Tsung-Yi Ho:
DLPlace: A Delay-Line Clocking-Based Placement Framework for AQFP Circuits. ICCAD 2023: 1-8 - [c146]Zhuolun He, Bei Yu:
Invited Paper: Heterogeneous Acceleration for Design Rule Checking. ICCAD 2023: 1-7 - [c145]Fuxing Huang, Duanxiang Liu, Xingquan Li, Bei Yu, Wenxing Zhu:
Handling Orientation and Aspect Ratio of Modules in Electrostatics-Based Large Scale Fixed-Outline Floorplanning. ICCAD 2023: 1-9 - [c144]Zehua Pei, Fangzhou Liu, Zhuolun He, Guojin Chen, Haisheng Zheng, Keren Zhu, Bei Yu:
AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search. ICCAD 2023: 1-9 - [c143]Ziyang Yu, Chen Bai, Shoubo Hu, Ran Chen, Taohai He, Mingxuan Yuan, Bei Yu, Martin D. F. Wong:
IT-DSE: Invariance Risk Minimized Transfer Microarchitecture Design Space Exploration. ICCAD 2023: 1-9 - [c142]Su Zheng, Lancheng Zou, Peng Xu, Siting Liu, Bei Yu, Martin D. F. Wong:
Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction. ICCAD 2023: 1-9 - [c141]Zhen Zhuang, Kai-Yuan Chao, Bei Yu, Tsung-Yi Ho, Martin D. F. Wong:
Multi-Product Optimization for 3D Heterogeneous Integration with D2W Bonding. ICCAD 2023: 1-9 - [c140]Wanli Chen, Xufeng Yao, Xinyun Zhang, Bei Yu:
Efficient Deep Space Filling Curve. ICCV 2023: 17479-17488 - [c139]Peng Xu, Lin Zhang, Xuanzhou Liu, Jiaqi Sun, Yue Zhao, Haiqin Yang, Bei Yu:
Do Not Train It: A Linear Neural Architecture Search of Graph Neural Networks. ICML 2023: 38826-38847 - [c138]Shui Jiang, Tsung-Wei Huang, Bei Yu, Tsung-Yi Ho:
SNICIT: Accelerating Sparse Neural Network Inference via Compression at Inference Time on GPU. ICPP 2023: 51-61 - [c137]Siting Liu, Yuan Pu, Peiyu Liao, Hongzhong Wu, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu:
FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler (Extended Abstract). IJCAI 2023: 6458-6462 - [c136]Chen Bai, Jiayi Huang, Xuechao Wei, Yuzhe Ma, Sicheng Li, Hongzhong Zheng, Bei Yu, Yuan Xie:
ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis. MICRO 2023: 268-282 - [c135]Zhuolun He, Haoyuan Wu, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, Bei Yu:
ChatEDA: A Large Language Model Powered Autonomous Agent for EDA. MLCAD 2023: 1-6 - [c134]Bei Yu:
Machine Learning in EDA: When and How. MLCAD 2023: 1-6 - [c133]Guyue Huang, Yang Bai, Liu Liu, Yuke Wang, Bei Yu, Yufei Ding, Yuan Xie:
ALCOP: Automatic Load-Compute Pipelining in Deep Learning Compiler for AI-GPUs. MLSys 2023 - [c132]Su Zheng, Haoyu Yang, Binwu Zhu, Bei Yu, Martin D. F. Wong:
LithoBench: Benchmarking AI Computational Lithography for Semiconductor Manufacturing. NeurIPS 2023 - [i62]Guojin Chen, Zehua Pei, Haoyu Yang, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields. CoRR abs/2303.08435 (2023) - [i61]Wenqian Zhao, Qi Sun, Yang Bai, Wenbo Li, Haisheng Zheng, Bei Yu, Martin D. F. Wong:
A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU. CoRR abs/2303.08999 (2023) - [i60]Guojin Chen, Ziyang Yu, Hongduo Liu, Yuzhe Ma, Bei Yu:
DevelSet: Deep Neural Level Set for Instant Mask Optimization. CoRR abs/2303.12529 (2023) - [i59]Wenqian Zhao, Xufeng Yao, Ziyang Yu, Guojin Chen, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
AdaOPC: A Self-Adaptive Mask Optimization Framework For Real Design Patterns. CoRR abs/2303.12723 (2023) - [i58]Zixiao Wang, Yunheng Shen, Wenqian Zhao, Yang Bai, Guojin Chen, Farzan Farnia, Bei Yu:
DiffPattern: Layout Pattern Generation via Discrete Diffusion. CoRR abs/2303.13060 (2023) - [i57]Guojin Chen, Haoyu Yang, Bei Yu:
GPU-accelerated Matrix Cover Algorithm for Multiple Patterning Layout Decomposition. CoRR abs/2303.14335 (2023) - [i56]Xinyun Zhang, Haochen Tan, Han Wu, Mingjie Zhan, Ding Liang, Bei Yu:
Towards Versatile and Efficient Visual Knowledge Injection into Pre-trained Language Models with Cross-Modal Adapters. CoRR abs/2305.07358 (2023) - [i55]Jiequan Cui, Zhuotao Tian, Zhisheng Zhong, Xiaojuan Qi, Bei Yu, Hanwang Zhang:
Decoupled Kullback-Leibler Divergence Loss. CoRR abs/2305.13948 (2023) - [i54]Peng Xu, Lin Zhang, Xuanzhou Liu, Jiaqi Sun, Yue Zhao, Haiqing Yang, Bei Yu:
Do Not Train It: A Linear Neural Architecture Search of Graph Neural Networks. CoRR abs/2305.14065 (2023) - [i53]Shixin Chen, Shanyi Li, Zhen Zhuang, Su Zheng, Zheng Liang, Tsung-Yi Ho, Bei Yu, Alberto L. Sangiovanni-Vincentelli:
Floorplet: Performance-aware Floorplan Framework for Chiplet Integration. CoRR abs/2308.01672 (2023) - [i52]Zhuolun He, Haoyuan Wu, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, Bei Yu:
ChatEDA: A Large Language Model Powered Autonomous Agent for EDA. CoRR abs/2308.10204 (2023) - [i51]Peiyu Liao, Yuxuan Zhao, Dawei Guo, Yibo Lin, Bei Yu:
Analytical Die-to-Die 3D Placement with Bistratal Wirelength Model and GPU Acceleration. CoRR abs/2310.07424 (2023) - [i50]Zixiao Wang, Farzan Farnia, Zhenghao Lin, Yunheng Shen, Bei Yu:
On the Evaluation of Generative Models in Distributed Learning Tasks. CoRR abs/2310.11714 (2023) - [i49]Jianlei Yang, Jiacheng Liao, Fanding Lei, Meichen Liu, Junyi Chen, Lingkun Long, Han Wan, Bei Yu, Weisheng Zhao:
TinyFormer: Efficient Transformer Design and Deployment on Tiny Devices. CoRR abs/2311.01759 (2023) - [i48]Haoyuan Wu, Xinyun Zhang, Peng Xu, Peiyu Liao, Xufeng Yao, Bei Yu:
p-Laplacian Adaptation for Generative Pre-trained Vision-Language Models. CoRR abs/2312.10613 (2023) - [i47]Shixin Chen, Su Zheng, Chen Bai, Wenqian Zhao, Shuo Yin, Yang Bai, Bei Yu:
SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design. CoRR abs/2312.11820 (2023) - 2022
- [j66]Haocheng Li, Wing-Kai Chow, Gengjie Chen, Bei Yu, Evangeline F. Y. Young:
Pin-Accessible Legalization for Mixed-Cell-Height Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(1): 143-154 (2022) - [j65]Ran Chen, Wei Zhong, Haoyu Yang, Hao Geng, Fan Yang, Xuan Zeng, Bei Yu:
Faster Region-Based Hotspot Detection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 669-680 (2022) - [j64]Wei Zhong, Shuxiang Hu, Yuzhe Ma, Haoyu Yang, Xiuyuan Ma, Bei Yu:
Deep Learning-Driven Simultaneous Layout Decomposition and Mask Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 709-722 (2022) - [j63]Tinghuan Chen, Qi Sun, Canhui Zhan, Changze Liu, Huatao Yu, Bei Yu:
Deep H-GCN: Fast Analog IC Aging-Induced Degradation Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 1990-2003 (2022) - [j62]Hao Geng, Yuzhe Ma, Qi Xu, Jin Miao, Subhendu Roy, Bei Yu:
High-Speed Adder Design Space Exploration via Graph Neural Processes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2657-2670 (2022) - [j61]Bentian Jiang, Lixin Liu, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young:
Neural-ILT 2.0: Migrating ILT to Domain-Specific and Multitask-Enabled Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2671-2684 (2022) - [j60]Hao Geng, Haoyu Yang, Lu Zhang, Fan Yang, Xuan Zeng, Bei Yu:
Hotspot Detection via Attention-Based Deep Layout Metric Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2685-2698 (2022) - [j59]Guojin Chen, Wanli Chen, Qi Sun, Yuzhe Ma, Haoyu Yang, Bei Yu:
DAMO: Deep Agile Mask Optimization for Full-Chip Scale. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9): 3118-3131 (2022) - [j58]Martin Rapp, Hussam Amrouch, Yibo Lin, Bei Yu, David Z. Pan, Marilyn Wolf, Jörg Henkel:
MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3162-3181 (2022) - [j57]Qi Xu, Hao Geng, Tianming Ni, Song Chen, Bei Yu, Yi Kang, Xiaoqing Wen:
Fortune: A New Fault-Tolerance TSV Configuration in Router-Based Redundancy Structure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3182-3187 (2022) - [j56]Xiaodong Wang, Changhao Yan, Yuzhe Ma, Bei Yu, Fan Yang, Dian Zhou, Xuan Zeng:
Analog Circuit Yield Optimization via Freeze-Thaw Bayesian Optimization Technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4887-4900 (2022) - [j55]Wei Li, Yuzhe Ma, Yibo Lin, Bei Yu:
Adaptive Layout Decomposition With Graph Embedding Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 5030-5042 (2022) - [j54]Qi Sun, Xufeng Yao, Arjun Ashok Rao, Bei Yu, Shiyan Hu:
Counteracting Adversarial Attacks in Autonomous Driving. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5193-5206 (2022) - [j53]Tinghuan Chen, Bin Duan, Qi Sun, Meng Zhang, Guoqing Li, Hao Geng, Qianru Zhang, Bei Yu:
An Efficient Sharing Grouped Convolution via Bayesian Learning. IEEE Trans. Neural Networks Learn. Syst. 33(12): 7367-7379 (2022) - [j52]Qi Sun, Tinghuan Chen, Siting Liu, Jianli Chen, Hao Yu, Bei Yu:
Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design. ACM Trans. Design Autom. Electr. Syst. 27(4): 31:1-31:27 (2022) - [j51]Yiyang Jiang, Fan Yang, Bei Yu, Dian Zhou, Xuan Zeng:
Efficient Layout Hotspot Detection via Neural Architecture Search. ACM Trans. Design Autom. Electr. Syst. 27(6): 62:1-62:16 (2022) - [c131]Xinyun Zhang, Binwu Zhu, Xufeng Yao, Qi Sun, Ruiyu Li, Bei Yu:
Context-Based Contrastive Learning for Scene Text Recognition. AAAI 2022: 3353-3361 - [c130]Hao Geng, Tinghuan Chen, Qi Sun, Bei Yu:
Techniques for CAD Tool Parameter Auto-tuning in Physical Synthesis: A Survey (Invited Paper). ASP-DAC 2022: 635-640 - [c129]Xufeng Yao, Yang Bai, Xinyun Zhang, Yuechen Zhang, Qi Sun, Ran Chen, Ruiyu Li, Bei Yu:
PCL: Proxy-based Contrastive Learning for Domain Generalization. CVPR 2022: 7087-7097 - [c128]Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Bei Yu, Yu Huang:
Functionality matters in netlist representation learning. DAC 2022: 61-66 - [c127]Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao:
Eventor: an efficient event-based monocular multi-view stereo accelerator on FPGA platform. DAC 2022: 331-336 - [c126]Qi Sun, Xinyun Zhang, Hao Geng, Yuxuan Zhao, Yang Bai, Haisheng Zheng, Bei Yu:
GTuner: tuning DNN computations on GPU via graph attention network. DAC 2022: 1045-1050 - [c125]Hao Geng, Qi Xu, Tsung-Yi Ho, Bei Yu:
PPATuner: pareto-driven tool parameter auto-tuning in physical design via gaussian process transfer learning. DAC 2022: 1237-1242 - [c124]Siting Liu, Peiyu Liao, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu:
FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler. DATE 2022: 760-765 - [c123]Zhen Zhuang, Genggeng Liu, Tsung-Yi Ho, Bei Yu, Wenzhong Guo:
TRADER: A Practical Track-Assignment-Based Detailed Router. DATE 2022: 766-771 - [c122]Haoyu Yang, Kit Fung, Yuxuan Zhao, Yibo Lin, Bei Yu:
Mixed-Cell-Height Legalization on CPU-GPU Heterogeneous Systems. DATE 2022: 784-789 - [c121]Peiyu Liao, Siting Liu, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu:
DREAMPlace 4.0: Timing-driven Global Placement with Momentum-based Net Weighting. DATE 2022: 939-944 - [c120]Shuyuan Sun, Yiyang Jiang, Fan Yang, Bei Yu, Xuan Zeng:
Efficient Hotspot Detection via Graph Neural Network. DATE 2022: 1233-1238 - [c119]Wanli Chen, Xinge Zhu, Guojin Chen, Bei Yu:
Efficient Point Cloud Analysis Using Hilbert Curve. ECCV (2) 2022: 730-747 - [c118]Zhuolun He, Yuzhe Ma, Bei Yu:
X-Check: CPU-Accelerated Design Rule Checking via Parallel Sweepline Algorithms. ICCAD 2022: 52:1-52:9 - [c117]Zhen Zhuang, Bei Yu, Kai-Yuan Chao, Tsung-Yi Ho:
Multi-Package Co-Design for Chiplet Integration. ICCAD 2022: 114:1-114:9 - [c116]Wenqian Zhao, Xufeng Yao, Ziyang Yu, Guojin Chen, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
AdaOPC: A Self-Adaptive Mask Optimization Framework for Real Design Patterns. ICCAD 2022: 123:1-123:9 - [c115]Liangjian Wen, Yi Zhu, Lei Ye, Guojin Chen, Bei Yu, Jianzhuang Liu, Chunjing Xu:
LayouTransformer: Generating Layout Patterns with Transformer via Sequential Pattern Modeling. ICCAD 2022: 124:1-124:9 - [c114]Binwu Zhu, Xinyun Zhang, Yibo Lin, Bei Yu, Martin D. F. Wong:
Efficient Design Rule Checking Script Generation via Key Information Extraction. MLCAD 2022: 77-82 - [i46]Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao:
Eventor: An Efficient Event-Based Monocular Multi-View Stereo Accelerator on FPGA Platform. CoRR abs/2203.15439 (2022) - [i45]Yilun Chen, Shijia Huang, Shu Liu, Bei Yu, Jiaya Jia:
DSGN++: Exploiting Visual-Spatial Relation for Stereo-based 3D Detectors. CoRR abs/2204.03039 (2022) - [i44]Xiaogang Xu, Yitong Yu, Nianjuan Jiang, Jiangbo Lu, Bei Yu, Jiaya Jia:
PVDD: A Practical Video Denoising Dataset with Real-World Dynamic Scenes. CoRR abs/2207.01356 (2022) - [i43]Wei Li, Ruxuan Li, Yuzhe Ma, Siu On Chan, David Z. Pan, Bei Yu:
Rethinking Graph Neural Networks for the Graph Coloring Problem. CoRR abs/2208.06975 (2022) - [i42]Jiequan Cui, Zhisheng Zhong, Zhuotao Tian, Shu Liu, Bei Yu, Jiaya Jia:
Generalized Parametric Contrastive Learning. CoRR abs/2209.12400 (2022) - [i41]Guyue Huang, Yang Bai, Liu Liu, Yuke Wang, Bei Yu, Yufei Ding, Yuan Xie:
Enabling Data Movement and Computation Pipelining in Deep Learning Compiler. CoRR abs/2210.16691 (2022) - 2021
- [j50]Haoyu Yang, Wei Zhong, Yuzhe Ma, Hao Geng, Ran Chen, Wanli Chen, Bei Yu:
VLSI mask optimization: From shallow to deep learning. Integr. 77: 96-103 (2021) - [j49]Xiaowei Xu, Xinyi Zhang, Bei Yu, Xiaobo Sharon Hu, Christopher Rowen, Jingtong Hu, Yiyu Shi:
DAC-SDC Low Power Object Detection Challenge for UAV Applications. IEEE Trans. Pattern Anal. Mach. Intell. 43(2): 392-403 (2021) - [j48]Tinghuan Chen, Bingqing Lin, Hao Geng, Shiyan Hu, Bei Yu:
Leveraging Spatial Correlation for Sensor Drift Calibration in Smart Building. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(7): 1273-1286 (2021) - [j47]Haoyu Yang, Shuhe Li, Cyrus Tabery, Bingqing Lin, Bei Yu:
Bridging the Gap Between Layout Pattern Sampling and Hotspot Detection via Batch Active Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(7): 1464-1475 (2021) - [j46]Yiyang Jiang, Fan Yang, Bei Yu, Dian Zhou, Xuan Zeng:
Efficient Layout Hotspot Detection via Binarized Residual Neural Network Ensemble. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(7): 1476-1488 (2021) - [j45]Haocheng Li, Satwik Patnaik, Mohammed Ashraf, Haoyu Yang, Johann Knechtel, Bei Yu, Ozgur Sinanoglu, Evangeline F. Y. Young:
Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 1995-2008 (2021) - [j44]Wei Li, Yuzhe Ma, Qi Sun, Lu Zhang, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan:
OpenMPL: An Open-Source Layout Decomposer. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(11): 2331-2344 (2021) - [j43]Guyue Huang, Jingbo Hu, Yifan He, Jialong Liu, Mingyuan Ma, Zhaoyang Shen, Juejian Wu, Yuanfan Xu, Hengrui Zhang, Kai Zhong, Xuefei Ning, Yuzhe Ma, Haoyu Yang, Bei Yu, Huazhong Yang, Yu Wang:
Machine Learning for Electronic Design Automation: A Survey. ACM Trans. Design Autom. Electr. Syst. 26(5): 40:1-40:46 (2021) - [c113]Tinghuan Chen, Qi Sun, Bei Yu:
Machine Learning in Nanometer AMS Design-for-Reliability : (Invited Paper). ASICON 2021: 1-4 - [c112]Wei Li, Yuxiao Qu, Gengjie Chen, Yuzhe Ma, Bei Yu:
TreeNet: Deep Point Cloud Embedding for Routing Tree Construction. ASP-DAC 2021: 164-169 - [c111]Zhuolun He, Peiyu Liao, Siting Liu, Yuzhe Ma, Yibo Lin, Bei Yu:
Physical Synthesis for Advanced Neural Network Processors. ASP-DAC 2021: 833-840 - [c110]Haoyu Yang, Shifan Zhang, Kang Liu, Siting Liu, Benjamin Tan, Ramesh Karri, Siddharth Garg, Bei Yu, Evangeline F. Y. Young:
Attacking a CNN-based Layout Hotspot Detector Using Group Gradient Method. ASP-DAC 2021: 885-891 - [c109]Tinghuan Chen, Qi Sun, Canhui Zhan, Changze Liu, Huatao Yu, Bei Yu:
Analog IC Aging-induced Degradation Estimation via Heterogeneous Graph Convolutional Networks. ASP-DAC 2021: 898-903 - [c108]Junzhe Cai, Changhao Yan, Yuzhe Ma, Bei Yu, Dian Zhou, Xuan Zeng:
NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling Synthesis. DAC 2021: 187-192 - [c107]Yifeng Xiao, Miaodi Su, Haoyu Yang, Jianli Chen, Jun Yu, Bei Yu:
Low-Cost Lithography Hotspot Detection with Active Entropy Sampling and Model Calibration. DAC 2021: 907-912 - [c106]Qi Sun, Tinghuan Chen, Siting Liu, Jin Miao, Jianli Chen, Hao Yu, Bei Yu:
Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design. DATE 2021: 46-51 - [c105]Hongjia Li, Mengshu Sun, Tianyun Zhang, Olivia Chen, Nobuyuki Yoshikawa, Bei Yu, Yanzhi Wang, Yibo Lin:
Towards AQFP-Capable Physical Design Automation. DATE 2021: 954-959 - [c104]Qi Sun, Chen Bai, Hao Geng, Bei Yu:
Deep Neural Network Hardware Deployment Optimization via Advanced Active Learning. DATE 2021: 1510-1515 - [c103]Siting Liu, Qi Sun, Peiyu Liao, Yibo Lin, Bei Yu:
Global Placement with Deep Learning-Enabled Explicit Routability Optimization. DATE 2021: 1821-1824 - [c102]Ziyang Yu, Guojin Chen, Yuzhe Ma, Bei Yu:
A GPU-enabled Level Set Method for Mask Optimization. DATE 2021: 1835-1838 - [c101]Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework. ICCAD 2021: 1-9 - [c100]Yang Bai, Xufeng Yao, Qi Sun, Bei Yu:
AutoGTCO: Graph and Tensor Co-Optimize for Image Recognition with Transformers on GPU. ICCAD 2021: 1-9 - [c99]Ran Chen, Shoubo Hu, Zhitang Chen, Shengyu Zhu, Bei Yu, Pengyun Li, Cheng Chen, Yu Huang, Jianye Hao:
A Unified Framework for Layout Pattern Analysis with Deep Causal Estimation. ICCAD 2021: 1-9 - [c98]Guojin Chen, Ziyang Yu, Hongduo Liu, Yuzhe Ma, Bei Yu:
DevelSet: Deep Neural Level Set for Instant Mask Optimization. ICCAD 2021: 1-9 - [c97]Hao Geng, Fan Yang, Xuan Zeng, Bei Yu:
When Wafer Failure Pattern Classification Meets Few-shot Learning and Self-Supervised Learning. ICCAD 2021: 1-8 - [c96]Zhuolun He, Ziyi Wang, Chen Bai, Haoyu Yang, Bei Yu:
Graph Learning-Based Arithmetic Block Identification. ICCAD 2021: 1-8 - [c95]Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu:
McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs. ICCAD 2021: 1-9 - [c94]Wenqian Zhao, Qi Sun, Yang Bai, Wenbo Li, Haisheng Zheng, Bei Yu, Martin D. F. Wong:
A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU. ICCAD 2021: 1-9 - [c93]Binwu Zhu, Ran Chen, Xinyun Zhang, Fan Yang, Xuan Zeng, Bei Yu, Martin D. F. Wong:
Hotspot Detection via Multi-task Learning and Transformer Encoder. ICCAD 2021: 1-8 - [c92]Jiequan Cui, Zhisheng Zhong, Shu Liu, Bei Yu, Jiaya Jia:
Parametric Contrastive Learning. ICCV 2021: 695-704 - [c91]Qi Sun, Chen Bai, Tinghuan Chen, Hao Geng, Xinyun Zhang, Yang Bai, Bei Yu:
Fast and Efficient DNN Deployment via Deep Gaussian Transfer Learning. ICCV 2021: 5360-5370 - [c90]Ruixing Wang, Xiaogang Xu, Chi-Wing Fu, Jiangbo Lu, Bei Yu, Jiaya Jia:
Seeing Dynamic Scene in the Dark: A High-Quality Video Dataset with Mechatronic Alignment. ICCV 2021: 9680-9689 - [c89]Wei Li, Guojin Chen, Haoyu Yang, Ran Chen, Bei Yu:
Learning Point Clouds in EDA. ISPD 2021: 55-62 - [i40]Guyue Huang, Jingbo Hu, Yifan He, Jialong Liu, Mingyuan Ma, Zhaoyang Shen, Juejian Wu, Yuanfan Xu, Hengrui Zhang, Kai Zhong, Xuefei Ning, Yuzhe Ma, Haoyu Yang, Bei Yu, Huazhong Yang, Yu Wang:
Machine Learning for Electronic Design Automation: A Survey. CoRR abs/2102.03357 (2021) - [i39]Haoyu Yang, Shuhe Li, Bei Yu:
Routing Towards Discriminative Power of Class Capsules. CoRR abs/2103.04278 (2021) - [i38]Jiequan Cui, Zhisheng Zhong, Shu Liu, Bei Yu, Jiaya Jia:
Parametric Contrastive Learning. CoRR abs/2107.12028 (2021) - [i37]Xiaogang Xu, Yi Wang, Liwei Wang, Bei Yu, Jiaya Jia:
Conditional Temporal Variational AutoEncoder for Action Video Prediction. CoRR abs/2108.05658 (2021) - [i36]Xiaoliu Luo, Zhuotao Tian, Taiping Zhang, Bei Yu, Yuan Yan Tang, Jiaya Jia:
PFENet++: Boosting Few-shot Semantic Segmentation with the Noise-filtered Context-aware Prior Mask. CoRR abs/2109.13788 (2021) - 2020
- [j42]Xingquan Li, Bei Yu, Jianli Chen, Wenxing Zhu:
DSA guiding template assignment with multiple redundant via and dummy via insertion. Integr. 70: 32-42 (2020) - [j41]Qi Xu, Song Chen, Hao Geng, Bo Yuan, Bei Yu, Feng Wu, Zhengfeng Huang:
Fault tolerance in memristive crossbar-based neuromorphic computing systems. Integr. 70: 70-79 (2020) - [j40]Haoyu Yang, Shuhe Li, Zihao Deng, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young:
GAN-OPC: Mask Optimization With Lithography-Guided Generative Adversarial Nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2822-2834 (2020) - [j39]Hao Geng, Wei Zhong, Haoyu Yang, Yuzhe Ma, Joydeep Mitra, Bei Yu:
SRAF Insertion via Supervised Dictionary Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2849-2859 (2020) - [j38]Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann:
TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4482-4495 (2020) - [j37]Yuzhe Ma, Wei Zhong, Shuxiang Hu, Jhih-Rong Gao, Jian Kuang, Jin Miao, Bei Yu:
A Unified Framework for Simultaneous Layout Decomposition and Mask Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5069-5082 (2020) - [j36]Qi Xu, Hao Geng, Song Chen, Bei Yu, Feng Wu:
Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D IC. ACM Trans. Design Autom. Electr. Syst. 25(1): 8:1-8:19 (2020) - [j35]Kang Liu, Haoyu Yang, Yuzhe Ma, Benjamin Tan, Bei Yu, Evangeline F. Y. Young, Ramesh Karri, Siddharth Garg:
Adversarial Perturbation Attacks on ML-based CAD: A Case Study on CNN-based Lithographic Hotspot Detection. ACM Trans. Design Autom. Electr. Syst. 25(5): 48:1-48:31 (2020) - [c88]Haoyu Yang, Wei Zhong, Yuzhe Ma, Hao Geng, Ran Chen, Wanli Chen, Bei Yu:
VLSI Mask Optimization: From Shallow To Deep Learning. ASP-DAC 2020: 434-439 - [c87]Wei Li, Jialu Xia, Yuzhe Ma, Jialu Li, Yibo Lin, Bei Yu:
Adaptive Layout Decomposition with Graph Embedding Neural Networks. DAC 2020: 1-6 - [c86]Wei Zhong, Shuxiang Hu, Yuzhe Ma, Haoyu Yang, Xiuyuan Ma, Bei Yu:
Deep Learning-Driven Simultaneous Layout Decomposition and Mask Optimization. DAC 2020: 1-6 - [c85]Wanli Chen, Xinge Zhu, Ruoqi Sun, Junjun He, Ruiyu Li, Xiaoyong Shen, Bei Yu:
Tensor Low-Rank Reconstruction for Semantic Segmentation. ECCV (17) 2020: 52-69 - [c84]Ran Chen, Yong Liu, Mengdan Zhang, Shu Liu, Bei Yu, Yu-Wing Tai:
Dive Deeper into Box for Object Detection. ECCV (22) 2020: 412-428 - [c83]Hao Geng, Haoyu Yang, Lu Zhang, Jin Miao, Fan Yang, Xuan Zeng, Bei Yu:
Hotspot Detection via Attention-based Deep Layout Metric Learning. ICCAD 2020: 16:1-16:8 - [c82]Guojin Chen, Wanli Chen, Yuzhe Ma, Haoyu Yang, Bei Yu:
DAMO: Deep Agile Mask Optimization for Full Chip Scale. ICCAD 2020: 19:1-19:9 - [c81]Bentian Jiang, Lixin Liu, Yuzhe Ma, Hang Zhang, Bei Yu, Evangeline F. Y. Young:
Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimization. ICCAD 2020: 20:1-20:9 - [c80]Qi Sun, Arjun Ashok Rao, Xufeng Yao, Bei Yu, Shiyan Hu:
Counteracting Adversarial Attacks in Autonomous Driving. ICCAD 2020: 83:1-83:7 - [c79]Zhuolun He, Yuzhe Ma, Lu Zhang, Peiyu Liao, Ngai Wong, Bei Yu, Martin D. F. Wong:
Learn to Floorplan through Acquisition of Effective Local Search Heuristics. ICCD 2020: 324-331 - [c78]Husheng Zhou, Wei Li, Zelun Kong, Junfeng Guo, Yuqun Zhang, Bei Yu, Lingming Zhang, Cong Liu:
DeepBillboard: systematic physical-world testing of autonomous driving systems. ICSE 2020: 347-358 - [c77]Junpeng Wang, Qi Xu, Bo Yuan, Song Chen, Bei Yu, Feng Wu:
Reliability-Driven Neural Network Training for Memristive Crossbar-Based Neuromorphic Computing Systems. ISCAS 2020: 1-4 - [c76]Yuzhe Ma, Zhuolun He, Wei Li, Lu Zhang, Bei Yu:
Understanding Graphs in EDA: From Shallow to Deep Learning. ISPD 2020: 119-126 - [i35]Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann:
TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix). CoRR abs/2003.00862 (2020) - [i34]Haocheng Li, Satwik Patnaik, Abhrajit Sengupta, Haoyu Yang, Johann Knechtel, Bei Yu, Evangeline F. Y. Young, Ozgur Sinanoglu:
Attacking Split Manufacturing from a Deep Learning Perspective. CoRR abs/2007.03989 (2020) - [i33]Ran Chen, Yong Liu, Mengdan Zhang, Shu Liu, Bei Yu, Yu-Wing Tai:
Dive Deeper Into Box for Object Detection. CoRR abs/2007.14350 (2020) - [i32]Wanli Chen, Xinge Zhu, Ruoqi Sun, Junjun He, Ruiyu Li, Xiaoyong Shen, Bei Yu:
Tensor Low-Rank Reconstruction for Semantic Segmentation. CoRR abs/2008.00490 (2020) - [i31]Guojin Chen, Wanli Chen, Yuzhe Ma, Haoyu Yang, Bei Yu:
DAMO: Deep Agile Mask Optimization for Full Chip Scale. CoRR abs/2008.00806 (2020)
2010 – 2019
- 2019
- [j34]Qianru Zhang, Meng Zhang, Tinghuan Chen, Zhifei Sun, Yuzhe Ma, Bei Yu:
Recent advances in convolutional neural network acceleration. Neurocomputing 323: 37-51 (2019) - [j33]Song Chen, Qi Xu, Bei Yu:
Adaptive 3D-IC TSV Fault Tolerance Structure Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(5): 949-960 (2019) - [j32]Derong Liu, Bei Yu, Vinicius S. Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, David Z. Pan:
Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1147-1160 (2019) - [j31]Haoyu Yang, Jing Su, Yi Zou, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young:
Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1175-1187 (2019) - [j30]Meng Li, Kaveh Shamsi, Travis Meade, Zheng Zhao, Bei Yu, Yier Jin, David Z. Pan:
Provably Secure Camouflaging Strategy for IC Protection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(8): 1399-1412 (2019) - [j29]Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan:
A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(9): 1585-1598 (2019) - [j28]Yuzhe Ma, Subhendu Roy, Jin Miao, Jiamin Chen, Bei Yu:
Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(12): 2298-2311 (2019) - [c75]Wei Li, Yuzhe Ma, Qi Sun, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan:
OpenMPL: An Open Source Layout Decomposer: Invited Paper. ASICON 2019: 1-4 - [c74]Haoyu Yang, Piyush Pathak, Frank Gennari, Ya-Chieh Lai, Bei Yu:
Detecting multi-layer layout hotspots with adaptive squish patterns. ASP-DAC 2019: 299-304 - [c73]Xingquan Li, Bei Yu, Jianli Chen, Wenxing Zhu:
A local optimal method on DSA guiding template assignment with redundant/dummy via insertion. ASP-DAC 2019: 305-310 - [c72]Hao Geng, Haoyu Yang, Yuzhe Ma, Joydeep Mitra, Bei Yu:
SRAF insertion via supervised dictionary learning. ASP-DAC 2019: 406-411 - [c71]Zheng Zhao, Derong Liu, Meng Li, Zhoufeng Ying, Lu Zhang, Biying Xu, Bei Yu, Ray T. Chen, David Z. Pan:
Hardware-software co-design of slimmed optical neural networks. ASP-DAC 2019: 705-710 - [c70]Yuzhe Ma, Haoxing Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan, Bei Yu:
High Performance Graph Convolutional Networks with Applications in Testability Analysis. DAC 2019: 18 - [c69]Tinghuan Chen, Bingqing Lin, Hao Geng, Bei Yu:
Sensor Drift Calibration via Spatial Correlation Model in Smart Building. DAC 2019: 105 - [c68]Haocheng Li, Satwik Patnaik, Abhrajit Sengupta, Haoyu Yang, Johann Knechtel, Bei Yu, Evangeline F. Y. Young, Ozgur Sinanoglu:
Attacking Split Manufacturing from a Deep Learning Perspective. DAC 2019: 135 - [c67]Ran Chen, Wei Zhong, Haoyu Yang, Hao Geng, Xuan Zeng, Bei Yu:
Faster Region-based Hotspot Detection. DAC 2019: 146 - [c66]Yiyang Jiang, Fan Yang, Hengliang Zhu, Bei Yu, Dian Zhou, Xuan Zeng:
Efficient Layout Hotspot Detection via Binarized Residual Neural Network. DAC 2019: 147 - [c65]Haoyu Yang, Piyush Pathak, Frank Gennari, Ya-Chieh Lai, Bei Yu:
DeePattern: Layout Pattern Generation with Transforming Convolutional Auto-Encoder. DAC 2019: 148 - [c64]Bentian Jiang, Xiaopeng Zhang, Ran Chen, Gengjie Chen, Peishan Tu, Wei Li, Evangeline F. Y. Young, Bei Yu:
FIT: Fill Insertion Considering Timing. DAC 2019: 221 - [c63]Qi Sun, Tinghuan Chen, Jin Miao, Bei Yu:
Power-Driven DNN Dataflow Optimization on FPGA. ICCAD 2019: 1-7 - [c62]Yuzhe Ma, Ran Chen, Wei Li, Fanhua Shang, Wenjian Yu, Minsik Cho, Bei Yu:
A Unified Approximation Framework for Compressing and Accelerating Deep Neural Networks. ICTAI 2019: 376-383 - [i30]Kang Liu, Haoyu Yang, Yuzhe Ma, Benjamin Tan, Bei Yu, Evangeline F. Y. Young, Ramesh Karri, Siddharth Garg:
Are Adversarial Perturbations a Showstopper for ML-Based CAD? A Case Study on CNN-Based Lithographic Hotspot Detection. CoRR abs/1906.10773 (2019) - [i29]Haoyu Yang, Wen Chen, Piyush Pathak, Frank Gennari, Ya-Chieh Lai, Bei Yu:
Automatic Layout Generation with Applications in Machine Learning Engine Evaluation. CoRR abs/1912.05796 (2019) - [i28]Yuzhe Ma, Ziyang Yu, Bei Yu:
CAD Tool Design Space Exploration via Bayesian Optimization. CoRR abs/1912.06460 (2019) - [i27]Haoyu Yang, Wei Zhong, Yuzhe Ma, Hao Geng, Ran Chen, Wanli Chen, Bei Yu:
VLSI Mask Optimization: From Shallow To Deep Learning. CoRR abs/1912.07254 (2019) - 2018
- [j27]Xiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu:
A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(1): 217-230 (2018) - [j26]Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan:
TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(1): 231-244 (2018) - [j25]Jin Miao, Meng Li, Subhendu Roy, Yuzhe Ma, Bei Yu:
SD-PUF: Spliced Digital Physical Unclonable Function. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(5): 927-940 (2018) - [j24]Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan:
MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1237-1250 (2018) - [j23]Yibo Lin, Bei Yu, Meng Li, David Z. Pan:
Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(8): 1574-1587 (2018) - [j22]Gengjie Chen, Chak-Wa Pui, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Evangeline F. Y. Young, Bei Yu:
RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 2022-2035 (2018) - [j21]Jian Kuang, Evangeline F. Y. Young, Bei Yu:
CRMA: Incorporating Cut Redistribution With Mask Assignment to Enable the Fabrication of 1-D Gridded Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 2036-2049 (2018) - [j20]Shiyan Hu, Bei Yu, Huafeng Yu:
IEEE Transactions on Sustainable Computing: Guest Editorial on Special Issue on Sustainable Cyber-Physical Systems. IEEE Trans. Sustain. Comput. 3(2): 58-59 (2018) - [j19]Xingquan Li, Bei Yu, Jiaojiao Ou, Jianli Chen, David Z. Pan, Wenxing Zhu:
Graph-Based Redundant Via Insertion and Guiding Template Assignment for DSA-MP. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2504-2517 (2018) - [c61]Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan:
A practical split manufacturing framework for Trojan prevention via simultaneous wire lifting and cell insertion. ASP-DAC 2018: 265-270 - [c60]Haoyu Yang, Shuhe Li, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young:
GAN-OPC: mask optimization with lithography-guided generative adversarial nets. DAC 2018: 131:1-131:6 - [c59]Haocheng Li, Wing-Kai Chow, Gengjie Chen, Evangeline F. Y. Young, Bei Yu:
Routability-driven and fence-aware legalization for mixed-cell-height circuits. DAC 2018: 150:1-150:6 - [c58]Grace Li Zhang, Bing Li, Bei Yu, David Z. Pan, Ulf Schlichtmann:
TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing. DATE 2018: 91-96 - [c57]Qi Xu, Song Chen, Bei Yu, Feng Wu:
Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D IC. ACM Great Lakes Symposium on VLSI 2018: 451-454 - [c56]Fengxian Jiao, Sheqin Dong, Bei Yu, Bing Li, Ulf Schlichtmann:
Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips. ISCAS 2018: 1-4 - [c55]Wei Ye, Meng Li, Kai Zhong, Bei Yu, David Z. Pan:
Power Grid Reduction by Sparse Convex Optimization. ISPD 2018: 60-67 - [c54]Hao Geng, Haoyu Yang, Bei Yu, Xingquan Li, Xuan Zeng:
Sparse VLSI Layout Feature Extraction: A Dictionary Learning Approach. ISVLSI 2018: 488-493 - [i26]Song Chen, Qi Xu, Bei Yu:
Adaptive 3D-IC TSV Fault Tolerance Structure Generation. CoRR abs/1803.02490 (2018) - [i25]Haoyu Yang, Shuhe Li, Cyrus Tabery, Bingqing Lin, Bei Yu:
Bridging the Gap Between Layout Pattern Sampling and Hotspot Detection via Batch Active Learning. CoRR abs/1807.06446 (2018) - [i24]Yuzhe Ma, Subhendu Roy, Jin Miao, Jiamin Chen, Bei Yu:
Cross-layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach. CoRR abs/1807.07023 (2018) - [i23]Qianru Zhang, Meng Zhang, Tinghuan Chen, Zhifei Sun, Yuzhe Ma, Bei Yu:
Recent Advances in Convolutional Neural Network Acceleration. CoRR abs/1807.08596 (2018) - [i22]Yuzhe Ma, Ran Chen, Wei Li, Fanhua Shang, Wenjian Yu, Minsik Cho, Bei Yu:
A Unified Approximation Framework for Deep Neural Networks. CoRR abs/1807.10119 (2018) - [i21]Xiaowei Xu, Xinyi Zhang, Bei Yu, Xiaobo Sharon Hu, Christopher Rowen, Jingtong Hu, Yiyu Shi:
DAC-SDC Low Power Object Detection Challenge for UAV Applications. CoRR abs/1809.00110 (2018) - [i20]Qi Sun, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan:
OpenMPL: An Open Source Layout Decomposer. CoRR abs/1809.07554 (2018) - [i19]Husheng Zhou, Wei Li, Yuankun Zhu, Yuqun Zhang, Bei Yu, Lingming Zhang, Cong Liu:
DeepBillboard: Systematic Physical-World Testing of Autonomous Driving Systems. CoRR abs/1812.10812 (2018) - 2017
- [j18]Bingqing Lin, Bei Yu:
Smart building uncertainty analysis via adaptive Lasso. IET Cyper-Phys. Syst.: Theory & Appl. 2(1): 42-48 (2017) - [j17]Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan:
Stitch aware detailed placement for multiple E-beam lithography. Integr. 58: 47-54 (2017) - [j16]Meikang Qiu, Saurabh Kumar Garg, Rajkumar Buyya, Bei Yu, Shiyan Hu:
Special Issue on Scalable Cyber-Physical Systems. J. Parallel Distributed Comput. 103: 1-2 (2017) - [j15]Vinicius S. Livramento, Derong Liu, Salim Chowdhury, Bei Yu, Xiaoqing Xu, David Z. Pan, José Luís Almada Güntzel, Luiz C. V. dos Santos:
Incremental Layer Assignment Driven by an External Signoff Timing Engine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1126-1139 (2017) - [j14]Yibo Lin, Bei Yu, Biying Xu, David Z. Pan:
Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1140-1152 (2017) - [j13]Qi Xu, Song Chen, Xiaodong Xu, Bei Yu:
Clustered Fault Tolerance TSV Planning for 3-D Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(8): 1287-1300 (2017) - [j12]Yibo Lin, Bei Yu, David Z. Pan:
High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(9): 1532-1544 (2017) - [j11]Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan:
Incremental Layer Assignment for Timing Optimization. ACM Trans. Design Autom. Electr. Syst. 22(4): 75:1-75:25 (2017) - [c53]Haoyu Yang, Jing Su, Yi Zou, Bei Yu, Evangeline F. Y. Young:
Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning. DAC 2017: 62:1-62:6 - [c52]Gengjie Chen, Jian Kuang, Zhiliang Zeng, Hang Zhang, Evangeline F. Y. Young, Bei Yu:
Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design. DAC 2017: 70:1-70:6 - [c51]Soumi Chattopadhyay, Ansuman Banerjee, Bei Yu:
A utility-driven data transmission optimization strategy in large scale cyber-physical systems. DATE 2017: 1619-1622 - [c50]Yuzhe Ma, Jhih-Rong Gao, Jian Kuang, Jin Miao, Bei Yu:
A unified framework for simultaneous layout decomposition and mask optimization. ICCAD 2017: 81-88 - [c49]Chak-Wa Pui, Gengjie Chen, Yuzhe Ma, Evangeline F. Y. Young, Bei Yu:
Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper). ICCAD 2017: 929-936 - [c48]Subhendu Roy, Yuzhe Ma, Jin Miao, Bei Yu:
A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders. ISLPED 2017: 1-6 - [c47]Hang Zhang, Fengyuan Zhu, Haocheng Li, Evangeline F. Y. Young, Bei Yu:
Bilinear Lithography Hotspot Detection. ISPD 2017: 7-14 - [c46]Jiaojiao Ou, Bei Yu, Xiaoqing Xu, Joydeep Mitra, Yibo Lin, David Z. Pan:
DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment. ISPD 2017: 91-98 - [c45]Bei Yu:
F1B: Algorithms, models and simulation for systems. SoCC 2017: 1 - [c44]Cheng Zhuo, Bei Yu, Di Gao:
Accelerating chip design with machine learning: From pre-silicon to post-silicon. SoCC 2017: 227-232 - [c43]Haoyu Yang, Yajun Lin, Bei Yu, Evangeline F. Y. Young:
Lithography hotspot detection: From shallow to deep learning. SoCC 2017: 233-238 - [c42]Yuzhe Ma, Xuan Zeng, Bei Yu:
Methodologies for layout decomposition and mask optimization: A systematic review. VLSI-SoC 2017: 1-6 - 2016
- [j10]Bei Yu, Xiaoqing Xu, Subhendu Roy, Yibo Lin, Jiaojiao Ou, David Z. Pan:
Design for manufacturability and reliability in extreme-scaling VLSI. Sci. China Inf. Sci. 59(6): 061406:1-061406:23 (2016) - [j9]Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, David Z. Pan:
PARR: Pin-Access Planning and Regular Routing for Self-Aligned Double Patterning. ACM Trans. Design Autom. Electr. Syst. 21(3): 42:1-42:21 (2016) - [j8]Bei Yu, Kun Yuan, Jhih-Rong Gao, Shiyan Hu, David Z. Pan:
EBL Overlapping Aware Stencil Planning for MCC System. ACM Trans. Design Autom. Electr. Syst. 21(3): 43:1-43:24 (2016) - [c41]Hang Zhang, Haoyu Yang, Bei Yu, Evangeline F. Y. Young:
VLSI layout hotspot detection based on discriminative feature extraction. APCCAS 2016: 542-545 - [c40]Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan:
Stitch aware detailed placement for multiple e-beam lithography. ASP-DAC 2016: 186-191 - [c39]Tetsuaki Matsunawa, Bei Yu, David Z. Pan:
Laplacian eigenmaps and bayesian clustering based layout pattern sampling and its applications to hotspot detection and OPC. ASP-DAC 2016: 679-684 - [c38]Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan:
Incremental layer assignment for critical path timing. DAC 2016: 85:1-85:6 - [c37]Xiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu:
MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed Router. ACM Great Lakes Symposium on VLSI 2016: 87-92 - [c36]Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan:
MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes. ICCAD 2016: 7 - [c35]Meng Li, Kaveh Shamsi, Travis Meade, Zheng Zhao, Bei Yu, Yier Jin, David Z. Pan:
Provably secure camouflaging strategy for IC protection. ICCAD 2016: 28 - [c34]Jin Miao, Meng Li, Subhendu Roy, Bei Yu:
LRR-DPUF: learning resilient and reliable digital physical unclonable function. ICCAD 2016: 46 - [c33]Hang Zhang, Bei Yu, Evangeline F. Y. Young:
Enabling online learning in lithography hotspot detection with information-theoretic feature optimization. ICCAD 2016: 47 - [c32]Jian Kuang, Evangeline F. Y. Young, Bei Yu:
Incorporating cut redistribution with mask assignment to enable 1D gridded design. ICCAD 2016: 48 - [c31]Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Peishan Tu, Hang Zhang, Evangeline F. Y. Young, Bei Yu:
RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs. ICCAD 2016: 67 - [c30]Jiaojiao Ou, Bei Yu, David Z. Pan:
Concurrent Guiding Template Assignment and Redundant via Insertion for DSA-MP Hybrid Lithography. ISPD 2016: 39-46 - [r1]Bei Yu, David Z. Pan:
Layout Decomposition for Triple Patterning. Encyclopedia of Algorithms 2016: 1062-1065 - 2015
- [j7]Bei Yu, Kun Yuan, Duo Ding, David Z. Pan:
Layout Decomposition for Triple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(3): 433-446 (2015) - [j6]Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan:
Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 699-712 (2015) - [j5]Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Yibo Lin, Zhuo Li, Charles J. Alpert, David Z. Pan:
Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 726-739 (2015) - [c29]Bei Yu, David Z. Pan, Tetsuaki Matsunawa, Xuan Zeng:
Machine learning and pattern matching in physical design. ASP-DAC 2015: 286-293 - [c28]Jiwoo Pak, Bei Yu, David Z. Pan:
Electromigration-aware redundant via insertion. ASP-DAC 2015: 544-549 - [c27]Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, David Z. Pan:
PARR: pin access planning and regular routing for self-aligned double patterning. DAC 2015: 28:1-28:6 - [c26]Yibo Lin, Bei Yu, David Z. Pan:
High performance dummy fill insertion with coupling and uniformity constraints. DAC 2015: 71:1-71:6 - [c25]David Z. Pan, Lars Liebmann, Bei Yu, Xiaoqing Xu, Yibo Lin:
Pushing multiple patterning in sub-10nm: are we ready? DAC 2015: 197:1-197:6 - [c24]Jiaojiao Ou, Bei Yu, Jhih-Rong Gao, David Z. Pan, Moshe Preil, Azat Latypov:
Directed Self-Assembly Based Cut Mask Optimization for Unidirectional Design. ACM Great Lakes Symposium on VLSI 2015: 83-86 - [c23]Wei Ye, Bei Yu, David Z. Pan, Yongchan Ban, Lars Liebmann:
Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line. ACM Great Lakes Symposium on VLSI 2015: 289-294 - [c22]Bei Yu, Derong Liu, Salim Chowdhury, David Z. Pan:
TILA: Timing-Driven Incremental Layer Assignment. ICCAD 2015: 110-117 - [c21]Yibo Lin, Bei Yu, Biying Xu, David Z. Pan:
Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict. ICCAD 2015: 396-403 - [i18]Bei Yu, Kun Yuan, Jhih-Rong Gao, David Z. Pan:
E-BLOW: E-Beam Lithography Overlapping aware Stencil Planning for MCC System. CoRR abs/1502.00621 (2015) - 2014
- [c20]Jhih-Rong Gao, Bei Yu, David Z. Pan:
Self-aligned double patterning layout decomposition with complementary e-beam lithography. ASP-DAC 2014: 143-148 - [c19]Jhih-Rong Gao, Xiaoqing Xu, Bei Yu, David Z. Pan:
MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction. DAC 2014: 52:1-52:6 - [c18]Bei Yu, David Z. Pan:
Layout Decomposition for Quadruple Patterning Lithography and Beyond. DAC 2014: 53:1-53:6 - [c17]Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan:
Self-aligned double patterning aware pin access and standard cell layout co-optimization. ISPD 2014: 101-108 - [i17]Bei Yu, Jhih-Rong Gao, David Z. Pan:
L-Shape based Layout Fracturing for E-Beam Lithography. CoRR abs/1402.2420 (2014) - [i16]Bei Yu, Jhih-Rong Gao, David Z. Pan:
Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting. CoRR abs/1402.2425 (2014) - [i15]Bei Yu, Kun Yuan, Jhih-Rong Gao, David Z. Pan:
E-BLOW: E-Beam Lithography Overlapping aware Stencil Planning for MCC System. CoRR abs/1402.2435 (2014) - [i14]Jhih-Rong Gao, Bei Yu, Ru Huang, David Z. Pan:
Self-Aligned Double Patterning Friendly Configuration for Standard Cell Library Considering Placement. CoRR abs/1402.2442 (2014) - [i13]Bei Yu, Kun Yuan, Boyang Zhang, Duo Ding, David Z. Pan:
Layout decomposition for triple patterning lithography. CoRR abs/1402.2459 (2014) - [i12]Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto:
Network flow-based simultaneous retiming and slack budgeting for low power design. CoRR abs/1402.2460 (2014) - [i11]Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto:
Floorplanning and Topology Generation for Application-Specific Network-on-Chip. CoRR abs/1402.2462 (2014) - [i10]Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, David Z. Pan:
Methodology for standard cell compliance and detailed placement for triple patterning lithography. CoRR abs/1402.2635 (2014) - [i9]Bei Yu, Yen-Hung Lin, Gerard Luk-Pat, Duo Ding, Kevin Lucas, David Z. Pan:
A High-Performance Triple Patterning Layout Decomposer with Balanced Density. CoRR abs/1402.2890 (2014) - [i8]Bei Yu, Sheqin Dong, Satoshi Goto:
Multi-Voltage and Level-Shifter Assignment Driven Floorplanning. CoRR abs/1402.2894 (2014) - [i7]Duo Ding, Bei Yu, David Z. Pan:
GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing. CoRR abs/1402.2899 (2014) - [i6]Duo Ding, Bei Yu, Joydeep Ghosh, David Z. Pan:
EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation. CoRR abs/1402.2904 (2014) - [i5]Yen-Hung Lin, Bei Yu, David Z. Pan, Yih-Lang Li:
TRIAD: a triple patterning lithography aware detailed router. CoRR abs/1402.2906 (2014) - [i4]Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto:
Voltage and Level-Shifter Assignment Driven Floorplanning. CoRR abs/1402.3149 (2014) - [i3]Jhih-Rong Gao, Bei Yu, David Z. Pan:
Lithography Hotspot Detection and Mitigation in Nanometer VLSI. CoRR abs/1402.3150 (2014) - [i2]Bei Yu, David Z. Pan:
Layout Decomposition for Quadruple Patterning Lithography and Beyond. CoRR abs/1404.0321 (2014) - [i1]Bei Yu, Subhendu Roy, Jhih-Rong Gao, David Z. Pan:
Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting (JM3 Special Session). CoRR abs/1408.0407 (2014) - 2013
- [j4]David Z. Pan, Bei Yu, Jhih-Rong Gao:
Design for Manufacturing With Emerging Nanolithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(10): 1453-1472 (2013) - [c16]Jhih-Rong Gao, Bei Yu, Duo Ding, David Z. Pan:
Lithography hotspot detection and mitigation in nanometer VLSI. ASICON 2013: 1-4 - [c15]Bei Yu, Jhih-Rong Gao, David Z. Pan:
L-shape based layout fracturing for e-beam lithography. ASP-DAC 2013: 249-254 - [c14]Bei Yu, Kun Yuan, Jhih-Rong Gao, David Z. Pan:
E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system. DAC 2013: 70:1-70:7 - [c13]Bei Yu, Yen-Hung Lin, Gerard Luk-Pat, Duo Ding, Kevin Lucas, David Z. Pan:
A high-performance triple patterning layout decomposer with balanced density. ICCAD 2013: 163-169 - [c12]Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, David Z. Pan:
Methodology for standard cell compliance and detailed placement for triple patterning lithography. ICCAD 2013: 349-356 - 2012
- [j3]Wei Zhong, Takeshi Yoshimura, Bei Yu, Song Chen, Sheqin Dong, Satoshi Goto:
Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips. IEICE Trans. Electron. 95-C(4): 534-545 (2012) - [j2]Kun Yuan, Bei Yu, David Z. Pan:
E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(2): 167-179 (2012) - [c11]Duo Ding, Bei Yu, Joydeep Ghosh, David Z. Pan:
EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation. ASP-DAC 2012: 263-270 - [c10]Duo Ding, Bei Yu, David Z. Pan:
GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing. ASP-DAC 2012: 621-626 - [c9]Yen-Hung Lin, Bei Yu, David Z. Pan, Yih-Lang Li:
TRIAD: A triple patterning lithography aware detailed router. ICCAD 2012: 123-129 - [c8]Bei Yu, Jhih-Rong Gao, Duo Ding, Yongchan Ban, Jae-Seok Yang, Kun Yuan, Minsik Cho, David Z. Pan:
Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper). ICCAD 2012: 240-242 - [c7]David Z. Pan, Jhih-Rong Gao, Bei Yu:
VLSI CAD for emerging nanolithography. VLSI-DAT 2012: 1-4 - 2011
- [c6]Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto:
Network flow-based simultaneous retiming and slack budgeting for low power design. ASP-DAC 2011: 473-478 - [c5]Bei Yu, Kun Yuan, Boyang Zhang, Duo Ding, David Z. Pan:
Layout decomposition for triple patterning lithography. ICCAD 2011: 1-8 - [c4]Wei Zhong, Bei Yu, Song Chen, Takeshi Yoshimura, Sheqin Dong, Satoshi Goto:
Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion. ISQED 2011: 144-149 - 2010
- [c3]Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto:
Floorplanning and topology generation for application-specific network-on-chip. ASP-DAC 2010: 535-540 - [c2]Tao Lin, Sheqin Dong, Bei Yu, Song Chen, Satoshi Goto:
A revisit to voltage partitioning problem. ACM Great Lakes Symposium on VLSI 2010: 115-118
2000 – 2009
- 2009
- [j1]Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto:
Voltage and Level-Shifter Assignment Driven Floorplanning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 2990-2997 (2009) - [c1]Bei Yu, Sheqin Dong, Satoshi Goto, Song Chen:
Voltage-island driven floorplanning considering level-shifter positions. ACM Great Lakes Symposium on VLSI 2009: 51-56
Coauthor Index
[j101] [j99] [j98] [j94] [j90] [j89] [c187] [c172] [i71] [j80] [j78] [j71] [j69] [c162] [c161] [c150] [c136] [i62] [i60] [i59] [j64] [j62] [j61] [j59] [j56] [j55] [c118] [c116] [i43] [j50] [j44] [j43] [c112] [c111] [c108] [c102] [c101] [c98] [i40] [j40] [j39] [j37] [j35] [c88] [c87] [c86] [c82] [c81] [c79] [c76] [i31] [j34] [j31] [j28] [c75] [c72] [c70] [c62] [i30] [i28] [i27] [j25] [c60] [i24] [i23] [i22] [c50] [c49] [c48] [c42]
[j95] [i69] [i66] [i63] [j58] [i43] [j44] [j38] [i35] [j32] [j30] [j29] [c75] [c71] [j26] [j24] [j23] [j19] [c61] [c58] [c55] [i20] [j17] [j15] [j14] [j12] [j11] [c46] [j10] [j9] [j8] [c40] [c39] [c38] [c36] [c35] [c30] [r1] [j7] [j6] [j5] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [i18] [c20] [c19] [c18] [c17] [i17] [i16] [i15] [i14] [i13] [i10] [i9] [i7] [i6] [i5] [i3] [i2] [i1] [j4] [c16] [c15] [c14] [c13] [c12] [j2] [c11] [c10] [c9] [c8] [c7] [c5]
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