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2020 – today
- 2023
[j7]Xi Chen
, Yizhe Hu, Teerachot Siriburanon, Jianglin Du, Robert Bogdan Staszewski, Anding Zhu:
A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain-Gate-Source for Low Flicker Phase Noise and I/Q Exactness. IEEE J. Solid State Circuits 58(7): 1945-1958 (2023)- 2022
- [j6]Jianglin Du, Yizhe Hu, Teerachot Siriburanon, Enis Kobal, Philip Quinlan, Anding Zhu, Robert Bogdan Staszewski:
A Compact 0.2-0.3-V Inverse-Class-F23 Oscillator for Low 1/f3 Noise Over Wide Tuning Range. IEEE J. Solid State Circuits 57(2): 452-464 (2022) - [j5]Yizhe Hu, Xi Chen, Teerachot Siriburanon, Jianglin Du, Vivek Govindaraj, Anding Zhu, Robert Bogdan Staszewski:
A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking. IEEE J. Solid State Circuits 57(2): 518-534 (2022) - [j4]Xi Chen, Yizhe Hu, Teerachot Siriburanon, Jianglin Du, Robert Bogdan Staszewski, Anding Zhu:
Flicker Phase-Noise Reduction Using Gate-Drain Phase Shift in Transformer-Based Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 973-984 (2022) - 2021
- [j3]Suoping Hu, Jianglin Du, Peng Chen, Hieu Minh Nguyen, Philip Quinlan, Teerachot Siriburanon, Robert Bogdan Staszewski:
A Type-II Phase-Tracking Receiver. IEEE J. Solid State Circuits 56(2): 427-439 (2021) - [j2]Jianglin Du, Teerachot Siriburanon, Yizhe Hu, Vivek Govindaraj, Robert Bogdan Staszewski:
A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL. IEEE J. Solid State Circuits 56(11): 3445-3457 (2021) - [j1]Ali Esmailiyan, Jianglin Du, Teerachot Siriburanon, Filippo Schembari, Robert Bogdan Staszewski:
Dickson-Charge-Pump-Based Voltage-to-Time Conversion for Time-Based ADCs in 28-nm CMOS. IEEE Open J. Circuits Syst. 2: 23-31 (2021) - [c4]Jianglin Du, Teerachot Siriburanon, Xi Chen, Yizhe Hu, Vivek Govindaraj, Anding Zhu, Robert Bogdan Staszewski:
A 24-31 GHz Reference Oversampling ADPLL Achieving FoMjitter-N of -269.3 dB. VLSI Circuits 2021: 1-2 - 2020
- [c3]Yizhe Hu, Xi Chen, Teerachot Siriburanon, Jianglin Du, Zhong Gao, Vivek Govindaraj, Anding Zhu, Robert Bogdan Staszewski:
17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM. ISSCC 2020: 276-278
2010 – 2019
- 2019
- [c2]Vivek Govindaraj, Jianglin Du, Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski:
DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization. APCCAS 2019: 81-84 - [c1]Jianglin Du, Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski:
A 0.3V, 35% Tuning-Range, 60kHz 1/f3-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS. CICC 2019: 1-4
Coauthor Index
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