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Alessio Santiccioli
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2020 – today
- 2023
- [j9]Francesco Buccoleri
, Simone Mattia Dartizio
, Francesco Tesolin
, Luca Avallone
, Alessio Santiccioli
, Agata Iesurum
, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi
, Andrea Bevilacqua
, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino
:
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner. IEEE J. Solid State Circuits 58(3): 634-646 (2023) - [j8]Francesco Tesolin
, Simone Mattia Dartizio
, Francesco Buccoleri
, Alessio Santiccioli
, Luca Bertulessi
, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino
:
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays. IEEE J. Solid State Circuits 58(9): 2466-2477 (2023) - 2022
- [j7]Mario Mercandelli
, Alessio Santiccioli
, Angelo Parisi
, Luca Bertulessi
, Dmytro Cherniak, Andrea L. Lacaita
, Carlo Samori
, Salvatore Levantino
:
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter. IEEE J. Solid State Circuits 57(2): 505-517 (2022) - [j6]Simone Mattia Dartizio
, Francesco Tesolin
, Mario Mercandelli
, Alessio Santiccioli
, Abanob Shehata
, Saleh Karman
, Luca Bertulessi
, Francesco Buccoleri
, Luca Avallone
, Angelo Parisi
, Andrea L. Lacaita
, Michael Peter Kennedy
, Carlo Samori
, Salvatore Levantino
:
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping. IEEE J. Solid State Circuits 57(6): 1723-1735 (2022) - [j5]Simone Mattia Dartizio
, Francesco Buccoleri
, Francesco Tesolin
, Luca Avallone
, Alessio Santiccioli
, Agata Iesurum
, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi
, Andrea Bevilacqua
, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino
:
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time. IEEE J. Solid State Circuits 57(12): 3538-3551 (2022) - [c7]Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum
, Giovanni Steffan, Andrea Bevilacqua
, Luca Bertulessi
, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino:
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler. CICC 2022: 1-2 - [c6]Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum
, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi
, Andrea Bevilacqua
, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino:
A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching. ISSCC 2022: 1-3 - 2021
- [j4]Luca Avallone
, Mario Mercandelli
, Alessio Santiccioli
, Michael Peter Kennedy
, Salvatore Levantino
, Carlo Samori
:
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2775-2786 (2021) - [c5]Mario Mercandelli
, Alessio Santiccioli, Simone Mattia Dartizio, Abanob Shehata
, Francesco Tesolin, Saleh Karman, Luca Bertulessi
, Francesco Buccoleri, Luca Avallone, Angelo Parisi
, Andrea Leonardo Lacaita
, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino:
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter. ISSCC 2021: 445-447 - [c4]Alessio Santiccioli, Mario Mercandelli
, Simone Mattia Dartizio, Francesco Tesolin, Saleh Karman, Abanob Shehata
, Luca Bertulessi
, Francesco Buccoleri, Luca Avallone, Angelo Parisi
, Dmytro Cherniak, Andrea L. Lacaita
, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino:
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays. ISSCC 2021: 456-458 - 2020
- [b1]Alessio Santiccioli:
High-efficiency inductorless frequency synthesis. Polytechnic University of Milan, Italy, 2020 - [j3]Alessio Santiccioli
, Mario Mercandelli
, Luca Bertulessi
, Angelo Parisi
, Dmytro Cherniak, Andrea L. Lacaita
, Carlo Samori
, Salvatore Levantino
:
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking. IEEE J. Solid State Circuits 55(12): 3349-3361 (2020) - [c3]Alessio Santiccioli, Mario Mercandelli
, Luca Bertulessi
, Angelo Parisi
, Dmytro Cherniak, Andrea Leonardo Lacaita
, Carlo Samori, Salvatore Levantino:
17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking. ISSCC 2020: 268-270 - [c2]Mario Mercandelli
, Alessio Santiccioli, Angelo Parisi
, Luca Bertulessi
, Dmytro Cherniak, Andrea Leonardo Lacaita
, Carlo Samori, Salvatore Levantino:
17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter. ISSCC 2020: 274-276
2010 – 2019
- 2019
- [j2]Alessio Santiccioli
, Mario Mercandelli
, Andrea L. Lacaita
, Carlo Samori
, Salvatore Levantino
:
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power. IEEE J. Solid State Circuits 54(11): 3149-3160 (2019) - [j1]Alessio Santiccioli
, Carlo Samori
, Andrea L. Lacaita
, Salvatore Levantino
:
Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(10): 3775-3785 (2019) - [c1]Alessio Santiccioli, Mario Mercandelli
, Andrea L. Lacaita
, Carlo Samori
, Salvatore Levantino:
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power. CICC 2019: 1-4
Coauthor Index
aka: Andrea Leonardo Lacaita
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last updated on 2024-05-08 21:01 CEST by the dblp team
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